NXP USA Inc. MC9S12XA512CAA

MC9S12XA512CAA  Description The MC9S12XD family will retain the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family. Based on an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12. The MC9S12XD family introduces the performance-boosting XGATE module. Using enhanced DMA functionality, this parallel processing module offloads the CPU by providing high-speed data processing and transfer between peripheral modules, RAM, Flash EEPROM, and I/O ports. Providing up to 80 MIPS of performance added to the CPU, the XGATE can access all peripherals, Flash EEPROM, and the RAM block.

MC9S12XA512CAA  Features HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’s model identical to MC9S12 – Instruction queue – Enhanced indexed addressing – Enhanced instruction set — EBI (external bus interface) — MMC (module mapping control) — INT (interrupt controller) — DBG (debug module to monitor HCS12X CPU and XGATE bus activity) — BDM (background debug mode) XGATE (peripheral coprocessor) — Parallel processing module offloads the CPU by providing high-speed data processing and transfer — Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports PIT (periodic interrupt timer) — Four timers with independent time-out periods — Time-out periods selectable between 1 and 224 bus clock cycles