NXP USA Inc. MPC565MZP56

MPC565CZP56  Features PowerPC? core with a floating point unit (FPU) and a burst buffer controller (BBC) Unified system integration unit (USIU), a flexible memory controller, and improved interrupt controller 1 Mbyte of Flash memory (UC3F) — Typical endurance of 100,000 write/erase cycles @ 25oC — Typical data retention of 100 years @ 25oC 36 Kbytes of static RAM (two CRAM modules) — 8 Kbytes of the normal access or overlay access (sixteen 512-byte regions) — 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B Three-time processor units (TPU3) — TPU3 A and TPU3 B are connected to DPTRAM AB (6 Kbytes) — TPU3 C is connected to DPTRAM C (4 Kbytes) A 22-timer channel modular I/O system (MIOS14) — Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM) Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C) Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with analog multiplexers (AMUX) for 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part.