NXP USA Inc. MCF5272CVM66

MCF5272CVM66  Description The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It also eliminates most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system. The SIM provides programmable circuits to perform address-decoding and chip selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, and power management features.

MCF5272CVM66  Features Static Version 2 ColdFire variable-length RISC processor — 32-bit address and data path on-chip — 66-MHz processor core and bus frequency — Sixteen general-purpose 32-bit data and address registers — Multiply-accumulate unit (MAC) for DSP and fast multiply operations On-chip memories — 4-Kbyte SRAM on CPU internal bus — 16-Kbyte ROM on CPU internal bus — 1-Kbyte instruction cache Power management — Fully-static operation with processor sleep and whole-chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used — Software-controlled disable of external clock input for virtually zero power consumption (low-power stop mode) Two universal asynchronous/synchronous receiver transmitters (UARTs) — Full-duplex operation — Based on MC68681 dual-UART (DUART) programming model — Flexible baud rate generator — Modem control signals available (CTS and RTS) — Processor interrupt and wakeup capability — Enhanced Tx, Rx FIFOs, 24 bytes each