NXP USA Inc. MC9S12E128CPVE

MCU 16-bit HCS12 HCS12 CISC 128KB Flash 2.5V/3.3V/5V Automotive 112-Pin LQFP Tray
HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 128KB (128K x 8) FLASH 112-LQFP (20x20)
S12E 16-Bit Mcu, Hcs12 Core, 128Kb Flash, 50Mhz, Qfp 112 Rohs Compliant: Yes
16BIT 128K FLASH MCU, SMD, LQFP112; Controller Family/Series:HCS12/S12X; Core Size:16bit; No. of I/O's:90; Program Memory Size:128 KB; EEPROM Memory Size:2KB; RAM Memory Size:8KB; CPU Speed:25MHz; Oscillator Type:External, Internal; No. of Timers:4; Peripherals:ADC, DAC, PWM, Timer; Embedded Interface Type:I2C, SCI, SPI; No. of PWM Channels:6; Digital IC Case Style:LQFP; Supply Voltage Range:2.35V to 2.75V, 2.97V to 5.5V; Operating Temperature Range:-40°C to 85°C; No. of Pins:112; MSL:MSL 3 - 168 hours; SVHC:No SVHC (18-Jun-2012); Clock Frequency:25MHz; Flash Memory Size:128KB; Interface:I2C, SCI, SPI; Interface:I2C, SCI, SPI; Interface Type:I2C, SCI, SPI; Logic Function Number:12E128; Memory Size:131072; Memory Type:FLASH; Microprocessor/Controller Features:IIC, SCI, SPI; No. of ADC Inputs:16; No. of Bits:16; No. of I/O's:91; Number of bits In Timer:16; Number of bits in ADC:10; Operating Temperature Max:85°C; Operating Temperature Min:-40°C; Package / Case:LQFP; Program Memory Size:128KB
Device Core = HCS12 / Data Bus Width Bit = 16 / Instruction Set Architecture = CISC / Family Name = S12E / Clock Frequency Max. MHz = 25 / Program Memory Type = Flash / Program Memory Size KB = 128 / RAM Memory Size KB = 8 / Interfaces = SCI / Interfaces = SPI / ADC Channels = 16 / ADC Resolution Bit = 10 / DAC Resolution Bit = 8 / Number of Programmable I/Os = 90 / Number of Timers/Counters = 3 / Supply Voltage Min. V = 3 / Supply Voltage Max. V = 5.5 / Operating Temperature Min. °C = -40 / Operating Temperature Max. °C = 85 / Package Type = LQFP / Pins = 112 / Mounting Type = SMD / MSL = Level-3 / Packaging = Tray / Length mm = 20 / Width mm = 20 / Height mm = 1.4 / Reflow Temperature Max. °C = 260
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module. Note that V04 of the ATD has an external trigger (ETRIG) function which is tied off and not available for use. Section 8 Clock Reset Generator (CRG) Block Description Consult the CRG Block Guide for information about the Clock and Reset Generator module.8.1 Device-specific information The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block Guide for voltage level specifications. 3F.8.1.1 XCLKS The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS -- Port E I/O Pin 7). Section 9 Digital to Analog Converter (DAC) Block Description There are two digital to analog converter modules (DAC0, DAC1). Consult the DAC Block Guide for information about the DAC Module.