NXP USA Inc. MC56F8006VWL

MC56F8006VWL Description
The MC56F8006VWL is a Digital Signal Controller. With three execution units working in parallel and a dual Harvard-style architecture, the 56800E core supports up to six operations per instruction cycle. The streamlined instruction set and MCU-style programming approach make it simple to create efficient, compact DSP and control programs. The instruction set is also very effective for C compilers, allowing for quick construction of control applications that are optimized. Program execution via internal memories is supported by the 56F8006/56F8002. Each instruction cycle can access two data operands from the on-chip data RAM. Depending on the peripheral arrangement, the 56F8006/56F8002 additionally provides up to 40 general-purpose input/output (GPIO) lines.

MC56F8006VWL Features
Four internal data buses
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
Single-cycle 16*16-bit parallel multiplier-accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter

MC56F8006VWL Applications
Motor control (ACIM, BLDC, PMSM, SR, and stepper)
Handheld power tools
Arc detection
Medical device/equipment
Instrumentation
Lighting ballast
Industrial control
Home appliances
Smart sensors
Fire and security systems
Switched-mode power supply and power management
Power metering