IDT, Integrated Device Technology Inc SSTE32882KA1AKG

Description
28bit 1:2 or 26bit 1:2 and 4bit 1:1 registering clock driver with parity
Designed for 1.25V, 1.35V, and 1.5V VDD operation
All inputs are 1.25V, 1.35V, and 1.5V CMOS compatible, except for reset (RESET) and MIRROR inputs which are LVCMOS
All outputs are 1.25V, 1.35V, and 1.5V CMOS edgecontrolled drivers optimized to drive single terminated 250Ω to 500Ω traces in DDR3 RDIMM applications, except for the opendrain error (ERROUT) output
Clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn, and QnODTn are designed with different strength and skew to compensate for different loading and equalize signal travel speed
Two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input:
QuadCS disabled: Two chip select inputs (DCSO and DCST) and two copies of each chip select output (QACSO, QACSI, QBCSO, and QBCSI)
QuadCS enabled: Four chip select inputs (DCS[3:0]) and four chip select outputs (QCS[3:0])
Highperformance, lowjitter, lowskew buffer that distributes a differential clock input (CK and CK) to four differential pairs of clock outputs (Yn and Yn) and one differential pair of feedback clock outputs (FBOUT and FBOUT)
Operates from a differential clock (CK and CK)
Data registered at the crossing of CK going high and CK going low
Data driven to corresponding device outputs if exactly one of the DCS[n:0] input signals is driven low
Output characteristics can be changed to match different DIMM net topologies
Timing can be changed to compensate for different flight time of signals within the target application
Power consumption reduced by disabling unused outputs
Accepts a parity bit from the memory controller on the parity (PAR IN) input
Compares parity bit with data received on the DIMMindependent data inputs (DAn, DBAn, DRAS, DCAS, and DWE)
Indicates parity error on the opendrain ERROUT pin (active low)
Even parity convention: Valid parity is defined as an even number of ones across the DIMMindependent data inputs combined with the parity input bit
RESET must be held in the low state during powerup to ensure defined outputs from the register before a stable clock has been supplied
Available in a 176ball BGA with 0.65mm ball pitch in a 11 x 20 grid
Pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing
Corresponding inputs placed to allow two devices to be placed backtoback for four Rank modules while the data inputs share the same vias
Each input and output located close to an associated no ball position or on the outer two rows to allow low cost via technology combined with the small 0.65mm ball pitch

Features
1.25V, 1.35V, and 1.5V VDD operation
28bit 1:2 or 26bit 1:2 and 4bit 1:1 registering clock driver with parity
Quad Chip Select Enable (QCSEN) input for two modes of operation
Highperformance, lowjitter, lowskew clock buffer
Differential clock input (CK and CK)
Four differential pairs of clock outputs (Yn and Yn)
One differential pair of feedback clock outputs (FBOUT and FBOUT)
Data registered at the crossing of CK going high and CK going low
Output characteristics can be changed to match different DIMM net topologies
Timing can be changed to compensate for different flight time of signals within the target application
Power consumption reduced by disabling unused outputs
Parity error detection
Opendrain ERROUT pin (active low)
Even parity convention
RESET input to ensure defined outputs from the register before a stable clock has been supplied
176ball BGA with 0.65mm ball pitch in a 11 x 20 grid
Pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing
Corresponding inputs placed to allow two devices to be placed backtoback for four Rank modules while the data inputs share the same vias
Each input and output located close to an associated no ball position or on the outer two rows to allow low cost via technology combined with the small 0.65mm ball pitch

Applications
DDR3 RDIMM applications