Texas Instruments SN74ALVC7813-40DL

FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP Tube
74ALVC7813 Width Tube 74ALVC fifo memory 25MHz 40muA 0.635mm 40ns
IC FIFO SYNC 64X18 20NS 56SSOP
IC 64X18 SYNC FIFO MEM 56-SSOP
IC REG LIN 5V 300MA 8DSO E-PAD
FIFO, 64X18, 20NS, SYNCHRONOUS
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.