Texas Instruments SN74ALVC7813-20DLR
- Part Number:
- SN74ALVC7813-20DLR
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3706978-SN74ALVC7813-20DLR
- Description:
- IC 64X18 SYNC FIFO MEM 56-SSOP
- Datasheet:
- SN74ALVC7813
Texas Instruments SN74ALVC7813-20DLR technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ALVC7813-20DLR.
- Mounting TypeSurface Mount
- Package / Case56-BSSOP (0.295, 7.50mm Width)
- Surface MountYES
- Operating Temperature0°C~70°C
- PackagingTape & Reel (TR)
- Series74ALVC
- JESD-609 Codee4
- Pbfree Codeyes
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations56
- Terminal FinishNICKEL PALLADIUM GOLD
- TechnologyCMOS
- Voltage - Supply3V~3.6V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Supply Voltage3.3V
- Terminal Pitch0.635mm
- JESD-30 CodeR-PDSO-G56
- FunctionSynchronous
- Current - Supply (Max)40μA
- Qualification StatusCOMMERCIAL
- Supply Voltage-Max (Vsup)3.6V
- Supply Voltage-Min (Vsup)3V
- Memory Size1.125K 64 x 18
- Access Time13ns
- Data Rate50MHz
- Organization64X18
- Memory Width18
- Memory Density1152 bit
- Parallel/SerialPARALLEL
- Bus DirectionalUni-Directional
- Retransmit CapabilityNo
- Programmable Flags SupportYes
- Output EnableYES
- Expansion TypeWidth
- Cycle Time20 ns
- Height Seated (Max)2.79mm
- Length18.415mm
- Width7.5mm
- RoHS StatusROHS3 Compliant
SN74ALVC7813-20DLR Overview
The 74ALVC series is a group of integrated circuits that operate with a supply voltage range of 3V to 3.6V. These circuits have a moisture sensitivity level (MSL) of 3, which means they can withstand exposure to ambient humidity for up to 168 hours. The JESD-609 code for these circuits is e4. They have a terminal finish of nickel palladium gold, which provides excellent conductivity and corrosion resistance. The terminal position is dual, allowing for easy connection to other components. The supply voltage is 3.3V, and the maximum supply voltage is 3.6V. These circuits have a memory size of 1.125K 64 x 18, meaning they can store a large amount of data. They also have a data rate of 50MHz, enabling fast and efficient data processing.
SN74ALVC7813-20DLR Features
1.125K 64 x 18 memory size
74ALVC series
SN74ALVC7813-20DLR Applications
There are a lot of Rochester Electronics, LLC SN74ALVC7813-20DLR FIFOs Memory applications.
Disk Controllers
SPI Bus Flash Memory Devices
Extended product life cycle
General Data Collection Applications at Low-Temperatures
Digital buffering
Temporary storage elements
Consumer
Data
Test Equipment
Seismic Data Collection at Extreme Temperatures
The 74ALVC series is a group of integrated circuits that operate with a supply voltage range of 3V to 3.6V. These circuits have a moisture sensitivity level (MSL) of 3, which means they can withstand exposure to ambient humidity for up to 168 hours. The JESD-609 code for these circuits is e4. They have a terminal finish of nickel palladium gold, which provides excellent conductivity and corrosion resistance. The terminal position is dual, allowing for easy connection to other components. The supply voltage is 3.3V, and the maximum supply voltage is 3.6V. These circuits have a memory size of 1.125K 64 x 18, meaning they can store a large amount of data. They also have a data rate of 50MHz, enabling fast and efficient data processing.
SN74ALVC7813-20DLR Features
1.125K 64 x 18 memory size
74ALVC series
SN74ALVC7813-20DLR Applications
There are a lot of Rochester Electronics, LLC SN74ALVC7813-20DLR FIFOs Memory applications.
Disk Controllers
SPI Bus Flash Memory Devices
Extended product life cycle
General Data Collection Applications at Low-Temperatures
Digital buffering
Temporary storage elements
Consumer
Data
Test Equipment
Seismic Data Collection at Extreme Temperatures
SN74ALVC7813-20DLR More Descriptions
MCU 8-bit/16-bit XMEGA AVR RISC 16KB Flash 1.8V/2.5V/3.3V 49-Pin VFBGA
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
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