IDT, Integrated Device Technology Inc M2061-11I622.0800

Description
The M2060/61/62 and M2065/66/67 are Voltage-Controlled SAW Oscillator (VCSO) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support FEC (Forward Error Correction) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables.

Features
Integrated SAW delay line; Output of 15 to 700 MHz
Low phase jitter <0.5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz)
Pin-selectable PLL divider ratios support FEC ratios
M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW pin) to adjust loop bandwidth
Hitless Switching (HS) options with or without Phase Build-out (PBO) available to enable SONET (GR-253)/SDH (G.813) MTIE and TDEV compliance during reference clock reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package

Applications
FEC clock ratio translation in 10Gb optical systems
SONET/SDH clock generation and distribution
Telecom and datacom equipment