Texas Instruments CDC857-2DGGG4
- Part Number:
- CDC857-2DGGG4
- Manufacturer:
- Texas Instruments
- Ventron No:
- 2980626-CDC857-2DGGG4
- Description:
- IC 2.5V PLL CLK-DRVR 48-TSSOP
- Datasheet:
- CDC857-2, CDC857-3
Texas Instruments CDC857-2DGGG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments CDC857-2DGGG4.
- Mounting TypeSurface Mount
- Package / Case48-TFSOP (0.240, 6.10mm Width)
- Surface MountYES
- Operating Temperature0°C~85°C
- PackagingTube
- JESD-609 Codee4
- Pbfree Codeyes
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)2 (1 Year)
- Number of Terminations48
- Terminal FinishNICKEL PALLADIUM GOLD
- Voltage - Supply2.3V~2.7V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage2.5V
- Terminal Pitch0.5mm
- Reach Compliance Codeunknown
- Reflow Temperature-Max (s)NOT SPECIFIED
- OutputSSTL-2
- Pin Count48
- JESD-30 CodeR-PDSO-G48
- Qualification StatusCOMMERCIAL
- Supply Voltage-Max (Vsup)2.7V
- Supply Voltage-Min (Vsup)2.3V
- Number of Circuits1
- Frequency (Max)167MHz
- InputLVTTL, SSTL-2
- Ratio - Input:Output1:10
- PLLYes with Bypass
- Differential - Input:OutputYes/Yes
- Propagation Delay (tpd)6 ns
- Divider/MultiplierNo/No
- RoHS StatusROHS3 Compliant
CDC857-2DGGG4 Overview
The Moisture Sensitivity Level (MSL) for this product is 2 (1 Year), indicating that it can withstand moderate levels of moisture for up to one year. The voltage supply range is 2.3V~2.7V, providing a stable and reliable power source. The terminal position is DUAL, allowing for versatile installation options. The terminal form is GULL WING, ensuring secure and efficient connections. This product has 1 function and a reflow temperature-max (s) that is not specified. The output is SSTL-2, providing high-speed and low-power performance. It is classified under JESD-30 Code R-PDSO-G48 and has a qualification status of COMMERCIAL, making it suitable for a wide range of commercial applications. Additionally, this product is ROHS3 compliant, meeting the latest environmental regulations.
CDC857-2DGGG4 Features
Available in the 48-TFSOP (0.240, 6.10mm Width)
Supply voltage of 2.5V
CDC857-2DGGG4 Applications
There are a lot of Rochester Electronics, LLC CDC857-2DGGG4 Clock Generators applications.
Tracking filters
Vector network analyzers (VNA)
Frequency Modulation (FM) stereo decoders
Ports
Phase modulation cellular systems
Frequency synthesis
Modems
Electronic countermeasures
HDD recorders
DVD recorders
The Moisture Sensitivity Level (MSL) for this product is 2 (1 Year), indicating that it can withstand moderate levels of moisture for up to one year. The voltage supply range is 2.3V~2.7V, providing a stable and reliable power source. The terminal position is DUAL, allowing for versatile installation options. The terminal form is GULL WING, ensuring secure and efficient connections. This product has 1 function and a reflow temperature-max (s) that is not specified. The output is SSTL-2, providing high-speed and low-power performance. It is classified under JESD-30 Code R-PDSO-G48 and has a qualification status of COMMERCIAL, making it suitable for a wide range of commercial applications. Additionally, this product is ROHS3 compliant, meeting the latest environmental regulations.
CDC857-2DGGG4 Features
Available in the 48-TFSOP (0.240, 6.10mm Width)
Supply voltage of 2.5V
CDC857-2DGGG4 Applications
There are a lot of Rochester Electronics, LLC CDC857-2DGGG4 Clock Generators applications.
Tracking filters
Vector network analyzers (VNA)
Frequency Modulation (FM) stereo decoders
Ports
Phase modulation cellular systems
Frequency synthesis
Modems
Electronic countermeasures
HDD recorders
DVD recorders
CDC857-2DGGG4 More Descriptions
PLL Clock Driver Single 66MHz to 167MHz 48-Pin TSSOP Tube
Gold DUAL Obsolete GULL WING PLL Clock Driver IC 0C~85C 6ns 0.5mm 12mA
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:2.3V to 2.7V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
Gold DUAL Obsolete GULL WING PLL Clock Driver IC 0C~85C 6ns 0.5mm 12mA
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:2.3V to 2.7V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
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