Texas Instruments CDC857-2DGG
- Part Number:
- CDC857-2DGG
- Manufacturer:
- Texas Instruments
- Ventron No:
- 2978751-CDC857-2DGG
- Description:
- IC 2.5V PLL CLK-DRVR 48-TSSOP
- Datasheet:
- CDC857-2, CDC857-3
Texas Instruments CDC857-2DGG technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments CDC857-2DGG.
- Contact PlatingGold
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case48-TFSOP (0.240, 6.10mm Width)
- Number of Pins48
- Weight223.195796mg
- Operating Temperature0°C~85°C
- PackagingTube
- JESD-609 Codee4
- Pbfree Codeno
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)2 (1 Year)
- Number of Terminations48
- ECCN CodeEAR99
- SubcategoryClock Drivers
- Voltage - Supply2.3V~2.7V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage2.5V
- Terminal Pitch0.5mm
- Frequency167MHz
- Base Part NumberCDC857
- OutputSSTL-2
- Pin Count48
- Number of Outputs10
- Operating Supply Voltage2.5V
- Supply Voltage-Max (Vsup)2.7V
- Supply Voltage-Min (Vsup)2.3V
- Number of Circuits1
- Nominal Supply Current12mA
- InputLVTTL, SSTL-2
- Ratio - Input:Output1:10
- PLLYes with Bypass
- Differential - Input:OutputYes/Yes
- Propagation Delay (tpd)6 ns
- Divider/MultiplierNo/No
- Radiation HardeningNo
- RoHS StatusROHS3 Compliant
- Lead FreeContains Lead
CDC857-2DGG Overview
The number of pins for this particular electronic component is 48, providing a sufficient amount of connections for various functions. The operating temperature range for this component is 0°C to 85°C, making it suitable for use in a wide range of environments. However, it is important to note that this part is now considered obsolete, meaning it may be difficult to find and may not be compatible with newer systems. The supply voltage for this component is 2.5V, with a maximum of 2.7V. It also has 10 outputs, allowing for multiple signals to be transmitted. The output type is SSTL-2, and the nominal supply current is 12mA. Additionally, this component is ROHS3 compliant, ensuring it meets the necessary environmental standards.
CDC857-2DGG Features
Available in the 48-TFSOP (0.240, 6.10mm Width)
Supply voltage of 2.5V
Operating supply voltage of 2.5V
CDC857-2DGG Applications
There are a lot of Texas Instruments CDC857-2DGG Clock Generators applications.
GPS systems
Electronic countermeasures
Cable television converter boxes
Reference signals to RF systems
Frequency synthesis
CPUs
Frequency Modulation (FM) stereo decoders
Symbol synchronization
Test equipment
VSAT (Small Ground Satellite Station)
The number of pins for this particular electronic component is 48, providing a sufficient amount of connections for various functions. The operating temperature range for this component is 0°C to 85°C, making it suitable for use in a wide range of environments. However, it is important to note that this part is now considered obsolete, meaning it may be difficult to find and may not be compatible with newer systems. The supply voltage for this component is 2.5V, with a maximum of 2.7V. It also has 10 outputs, allowing for multiple signals to be transmitted. The output type is SSTL-2, and the nominal supply current is 12mA. Additionally, this component is ROHS3 compliant, ensuring it meets the necessary environmental standards.
CDC857-2DGG Features
Available in the 48-TFSOP (0.240, 6.10mm Width)
Supply voltage of 2.5V
Operating supply voltage of 2.5V
CDC857-2DGG Applications
There are a lot of Texas Instruments CDC857-2DGG Clock Generators applications.
GPS systems
Electronic countermeasures
Cable television converter boxes
Reference signals to RF systems
Frequency synthesis
CPUs
Frequency Modulation (FM) stereo decoders
Symbol synchronization
Test equipment
VSAT (Small Ground Satellite Station)
CDC857-2DGG More Descriptions
PLL Clock Driver Single 66MHz to 167MHz 48-Pin TSSOP Tube
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:2.3V to 2.7V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:2.3V to 2.7V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.
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