IDT, Integrated Device Technology Inc 8SLVP1208ANBGI/W

Description
The 8SLVP1208 is a highperformance differential LVPECL fanout buffer designed for fanning out highfrequency, low additive phasenoise clock and data signals. It operates from 3.3V and 2.5V power supplies and features guaranteed outputtooutput and parttopart skew characteristics, making it ideal for clock distribution applications requiring welldefined performance and repeatability. The device has two selectable differential inputs and eight low skew outputs. Integrated bias voltage generators enable easy interfacing of singleended signals to the device inputs. The 8SLVP1208 is optimized for low power consumption and low additive phase jitter.

Features
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept LVDS, LVPECL, and CML input levels
Maximum input clock frequency: 2GHz
LVCMOS interface levels for control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum) (fREF = 156.25MHz, Vpp = 1V, 12kHz20MHz)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (EE): 141mA
Available in leadfree (RoHS 6), 28Lead VFQFN package
40°C to 85°C ambient operating temperature
Supports case temperatures ≤ 105°C operations
Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also accept singleended LVCMOS levels

Applications
Clock distribution in highspeed systems
Data transmission in highspeed networks
Test and measurement equipment
Telecommunications systems
Wireless infrastructure