IDT, Integrated Device Technology Inc 8SLVP1102ANLGI

Description
The IDT8SLVP11021 is a highperformance differential LVPECL fanout buffer designed for fanning out highfrequency, very low additive phasenoise clock and data signals. It operates from a 3.3V or 2.5V power supply and features guaranteed outputtooutput and parttopart skew characteristics, making it ideal for clock distribution applications requiring welldefined performance and repeatability. The device has one differential input and two low skew outputs. An integrated bias voltage reference enables easy interfacing of singleended signals to the device input. The IDT8SLVP11021 is optimized for low power consumption and low additive phase noise.

Features
Two low skew, low additive jitter LVPECL output pairs
Differential PCLK, nPCLK pair can accept LVDS, LVPECL, CML differential input levels
Maximum input clock frequency: 2GHz
Output skew: 5ps (typical)
Propagation delay: 250ps (maximum)
Low additive phase jitter, RMS; REF = 156.25MHz, Vpp = 1V:
12kHz 20MHz: 49fs (maximum)
Full 3.3V or 2.5V supply voltage
Maximum device current consumption (EE): 34mA (maximum)
Available in leadfree (RoHS 6), 16Lead VFQFN package
40°C to 85°C ambient operating temperature
Differential PCLKA, NPCLKA and PCLKB, nPCLKB pairs can also accept singleended LVCMOS levels

Applications
Wiring the Differential Input Levels to Accept Singleended Levels (Figure 1A and Figure 1B)