IDT, Integrated Device Technology Inc 8SLVD1204-33NLGI

Description
The 8SLVD120433 is a highperformance differential LVDS fanout buffer designed for the fanout of highfrequency, very low additive phasenoise clock and data signals. It operates from a 3.3V power supply and features two selectable differential inputs and four low skew outputs. The integrated bias voltage reference enables easy interfacing of singleended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features
Four low skew, low additive jitter LVDS output pairs
Two selectable differential clock input pairs
Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (maximum)
Propagation delay: 310ps (maximum)
Low additive phase jitter, RMS: FREF=156.25MHz, Vpp = 1V, 10kHz20MHz: 100fs (maximum)
Full 3.3V supply voltage
Leadfree (RoHS 6), 16Lead VFQFN packaging
40°C to 85°C ambient operating temperature

Applications
Clock distribution
Data distribution
Highspeed data transmission
Telecommunications
Networking
Test and measurement