SN74SSTUB32864NMJR
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Texas Instruments SN74SSTUB32864NMJR

Part Number:
SN74SSTUB32864NMJR
Manufacturer:
Texas Instruments
Ventron No:
6380039-SN74SSTUB32864NMJR
Description:
410-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs
ECAD Model:
Datasheet:
sn74sstub32864
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Delivery:
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Specifications
Texas Instruments SN74SSTUB32864NMJR technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74SSTUB32864NMJR.
  • Function

    Function refers to the primary purpose or role of an electronic component within a circuit. It describes the specific task or operation that the component is designed to perform. For example, a resistor's function is to limit current flow, a capacitor's function is to store electrical energy, and a transistor's function is to amplify or switch signals. Understanding the function of a component is crucial for selecting the appropriate component for a particular application and ensuring its proper operation within the circuit.

    Memory interface
  • Output frequency (max) (MHz)
    410
  • Number of outputs

    Number of Outputs refers to the number of independent output signals or channels that an electronic component can provide. It indicates the capability of the component to drive multiple external devices or circuits simultaneously. A higher number of outputs allows for greater flexibility and connectivity in electronic systems.

    25
  • Output supply voltage (V)
    1.8
  • Core supply voltage (V)
    1.8
  • Features
    DDR2 register
  • Operating temperature range (°C)
    -40 to 85
  • Rating
    Catalog
  • Output type

    Output type refers to the type of signal or power that an electronic component can produce. It can be analog or digital, AC or DC, and can vary in voltage, current, or power levels. The output type is determined by the component's design and is crucial for matching it with other components in a circuit. Understanding the output type ensures proper signal processing, power delivery, and overall system functionality.

    SSTL-18
  • Input type

    Input Type refers to the type of signal that an electronic component can accept as input.

    SSTL-18
Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTUB32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTUB32864 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level.

The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and gates the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn outputs low. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input should be pulled up to VCC through a pullup resistor.

The two VREF pins (A3 and T3) are connected together internally by approximately 150. However, it isnecessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

SN74SSTUB32864NMJR More Descriptions
410-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs 96-NFBGA -40 to 85
IC CONFIG REG BUFF 25BIT 96-BGA
OEMs, CMs ONLY (NO BROKERS)
Certification
  • ISO 9001
  • ISO 13485
  • ISO 45001
  • ASA
  • ESD
  • DUNS
  • SMTA
  • ROHS

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