IDT, Integrated Device Technology Inc 8534AY-01LFT

Description
The 853401 is a low skew, 1to22 Differentialto3.3V LVPECL Fanout Buffer. It has two selectable clock inputs: CLK, nCLK and PCLK, nPCLK. The CLK, nCLK pair can accept most standard differential input levels, while the PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. Its low output and parttopart skew characteristics make it ideal for workstation, server, and other highperformance clock distribution applications.

Features
Twentytwo differential LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 100ps (maximum)
Translates any singleended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
Additive phase jitter, RMS): 0.15ps (typical)
Full 3.3V supply mode
0°C to 85°C ambient operating temperature
Available in leadfree (RoHS 6) package

Applications
Workstation
Server
Other highperformance clock distribution applications