74LS161 4-BIt Synchronous Counter Functions and Applications
22 April 2024
Ⅲ. Working principle of 74LS161
Ⅴ. Basic applications of 74LS161
Ⅵ. How to choose the appropriate 74LS161 counter?
Ⅶ. The difference between 74LS161 and 74LS163
The 74LS161 is a counter manufactured by Fairchild and belongs to the 74LS series. It is a commonly used four-bit binary presettable synchronous addition counter with internal feed overrun and fast counting. This counter mainly consists of a clock controller, three basic RS flip-flops and a number of 8-bit binary counter units. 74LS161 counter can be flexibly applied to a variety of digital circuits as well as microcontroller systems to realize a variety of important functions such as frequency divider. Its synchronization preset and clear function makes it widely used in digital logic design.
The diagram depicted above illustrates the pin configuration for the 74LS161 chip. Below are the names and descriptions of each pin.
• PE’: Parallel enable (active low) input
• P0-P3: Parallel inputs
• CEP: Count enable parallel input
• CET: Count enable trickle input
• CP: Clock (active high going edge) input
• MR: Master reset (active low) input
• SR: Synchronous reset (active low) input
• Q0-Q3: Parallel outputs
• TC: Terminal count output
74LS161 is a 4-bit binary synchronous counter, which can realize the counting function from 0000 to 1111. Its working principle is based on the clock signal as well as the input of the control pin. The 74LS161 has two clock input pins, CP1 and CP2. Among them, CP1 is used for forward counting, and CP2 is used for reverse counting. According to the level changes of CP1 and CP2, the value of the counter will increase or decrease accordingly. Since the 74LS161 is a synchronous counter, its counting is synchronized with the edge of the clock signal. Specifically, the counter value only changes on the rising or falling edge of the clock signal. This design is because the edge of the clock signal is stable, thus ensuring that the counter can operate correctly at the edge moment.
The 74LS161 is also equipped with a reset pin (MR) which is used to reset the counter value to 0000. When the MR pin receives a low level signal, the counter is cleared. This is an asynchronous reset and is not controlled by a clock signal. In addition to the clock and reset signals, the 74LS161 also has an enable pin (CE). When the CE pin receives a low level signal, the counter value will be frozen, that is, counting will stop. This enable signal can flexibly control the start and stop of the counter, providing convenience for various application scenarios.
It can be seen from the function table of 74LS161 that when the clearing terminal CR is "0", the counter outputs Q3, Q2, Q1, and Q0 will immediately change to all "0". At this time, the counter performs an asynchronous reset function. When CR is "1" and LD is "0", under the action of the rising edge of the CP signal, the state of the 74LS161 outputs Q3, Q2, Q1 and Q0 will be identical with the state of the parallel data inputs D3, D2, D1 and D0. This reflects its synchronized number setting function. Only when CR, LD, EP, ET are "1", and under the action of the rising edge of the CP pulse, the counter will carry out the add 1 operation. In addition, the 74LS161 is also equipped with a feed output CO, its logical relationship is CO=Q0·Q1·Q2·Q3·CET. Through the use of the counter's zero and set the number of functions, a piece of 74LS161 can be constructed into a hexadecimal frequency divider, so as to meet the needs of a variety of digital circuits and system design.
1.16-bit base counter
2. Arbitrary base counter
There are two methods to implement arbitrary base, namely feedback setting and feedback clearing.
(1) Feedback setting
The feedback setting is to connect the data output terminal Q through the NAND gate back to the parallel enable control terminal LD (usually marked as LOAD in the figure). Since the parallel enable control terminal LD is used, we also need to use the data input terminals A0 to A3 (which may be marked D0 to D3 in the simulation diagram). If no signal is connected to the input, we cannot determine the required base number. Taking hexadecimal as an example, if the input of terminal A is 0000 (that is, there are 12 states from 0000 to 1011), when the output of terminal Q is 1011 (that is, Q3, Q2, and Q0 are 1), after passing through the NAND gate, LD will be 0. At this time, it also needs to wait for a CP clock signal to synchronously set 0000 on the A terminal to the Q terminal, that is, completing the 12-state cycle (0000 to 1011). Under this connection method, the state of 1011 is stable. If the input of terminal A is 0001, the final output of terminal Q will be 1100, forming 12 state cycles from 0001 to 1100. Similarly, if the input of terminal A is 0100, the final output of terminal Q will be 1111, forming 12 state cycles from 0100 to 1111. In addition, it should be noted that when the Q terminal output is 1111, a carry will occur, and the RCO terminal (carry output terminal) will be 1 at this time. Therefore, we can directly connect the RCO terminal to a NOT gate, and then connect it back to the parallel enable control terminal LD to use the carry signal to realize automatic feedback setting. In this way, the counter can automatically count in cycles according to the preset base number.
If the required base is greater than 16, multiple 74LS161s will be needed to achieve it. The method is to connect the low-order carry terminal to the high-order CTP and CTT terminals (ENP and ENT in the simulation diagram). The chips must share the CP clock signal. The 32-digit simulation is released here. If you need other counts greater than 16-digit, please refer to the feedback clearing and feedback pointing methods below.
(2) Feedback clearing
Feedback clearing refers to connecting the data output terminal Q back to the clearing terminal RD' (usually marked MR in the simulation diagram) through the NAND gate. Taking the implementation of hexadecimal system (a total of 12 states from 0000 to 1011) as an example, we need to pass the most significant bit (i.e. Q3Q2) in the binary representation of 12+1 (i.e. a total of 13 states from 0000 to 1100) through the NAND gate Then connect it back to the clearing terminal RD'. So, why do we need to add 1 to the required base number before connecting the clearing terminal RD'? This is because 74LS161 has the property of asynchronous clearing, that is, when RD' receives a low level, it does not need to wait for the clock signal of CP, and the clearing function will be triggered immediately. If we use 1011 as the hexadecimal feedback clearing condition, when Q3Q2Q0 is 1, passing through the NAND gate will cause RD' to immediately change to 0 (valid), which will immediately trigger the clearing function. Therefore, the state 1011 is not saved and is not included in the count. In order to avoid this situation, we need to use 1011+1 or 1100 as the condition for feedback clearing.
We can choose a suitable 74LS161 counter according to the following steps. First of all, we need to define the required counting range. 74LS161 is a 4-bit binary counter that can count from 0 to 15 (i.e., 0 to F in hexadecimal). If a larger count range is required, consider cascading multiple 74LS161 counters. Secondly, the 74LS161 has asynchronous zero and synchronous counting functions. Depending on the specific application requirements, we need to determine whether we need to use its asynchronous zero or synchronous counting function. If other special counting modes are required, it may be necessary to consider other types of counters or to combine them with other logic circuits. Then, we need to determine the frequency of the clock signal required for the application. 74LS161's clock input port (usually labeled CP or CLK) is capable of receiving an external clock signal and counting based on the rising edge of the clock signal. It is critical to ensure that the selected clock signal frequency matches the counter's counting speed. Next, depending on the application requirements, we need to determine the desired output signals. the 74LS161 has four output ports (Q0 through Q3) which provide the current count value of the counter. If the application requires other types of output signals (e.g., BCD code outputs), additional logic circuitry may need to be used to convert the output signals. Finally, we need to make sure that the 74LS161 counter selected meets the power supply requirements and that its package type is compatible with the board. This involves consideration of the counter's operating voltage, power consumption, and physical size to ensure that they can be smoothly integrated into our circuit.
The 74LS161 is a 4-bit synchronous binary counter while the 74LS163 is a 4-bit synchronous binary counter and parallel loader. Specific differences are as follows.
1. Different pins: 74LS161 and 74LS163 have different pin arrangement. 74LS161 has 16 pins while 74LS163 has 14 pins.
2. Different functions: The 74LS161 serves solely as a counter, performing counting operations exclusively, whereas the 74LS163 not only counts but also incorporates a parallel loading function.
3. Different operating modes: 74LS161 can only perform binary counting, while 74LS163 can perform binary and BCD counting.
Therefore, although 74LS161 and 74LS163 are both 4-bit synchronous binary counters, they have different pins, functions and operating modes.
Frequently Asked Questions
1. What is a 4-bit synchronous counter?
A 4-bit Synchronous up counter start to count from 0 (0000 in binary) and increment or count upwards to 15 (1111 in binary) and then start new counting cycle by getting reset.
2. How does a 4-bit counter work?
A 4-bit binary up/down counter cycles through a sequence that ranges from 0000 to 1111 and then reverses from 1111 back to 0000. If the external input labeled 'UP' is set to 1, irrespective of the 'DOWN' input status, the circuit functions as a UP counter, iterating through a sequence from 0000 to 1111.
3. What is the function of the 74LS161?
The 74LS161 is a 4-bit binary counter IC (Integrated Circuit) with synchronous reset. It counts up or down depending on the clock input and control signals.
