Texas Instruments SN74AUP1G80DCKT

SN74AUP1G80DCKT Overview
In the form of 5-TSSOP, SC-70-5, SOT-353, it has been packaged. D flip flop is included in the Tape & Reel (TR)package. There is a Invertedoutput configured with it. There is a trigger configured with Positive Edge. This electronic part is mounted in the way of Surface Mount. A 0.8V~3.6Vsupply voltage is required for it to operate. Currently, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. It belongs to the 74AUPseries of FPGAs. There should be no greater frequency than 260MHzon its output. During its operation, it consumes 0.9μA quiescent energy. A total of 5 terminations have been made. D latch belongs to the 74AUP1G80 family. A voltage of 1.2V provides power to the D latch. The input capacitance of this JK flip flopis 1.5pF farads. An electronic device belonging to the family AUP/ULP/Vcan be found here. This electronic part is mounted in the way of Surface Mount. A total of 5pins are provided on this board. This device's clock edge trigger type is Positive Edge. The part you are looking for is included in FF/Latches. An electronic part with 1bits has been designed. In this case, the maximum supply voltage (Vsup) reaches 3.6V. For normal operation, the supply voltage (Vsup) should be kept above 0.8V. In order to achieve its superior flexibility, 1 circuits are used. Considering the reliability of this T flip flop, it is well suited for TR. Featuring the maximum design flexibility, it has an output current of 4mA .

SN74AUP1G80DCKT Features
Tape & Reel (TR) package
74AUP series
5 pins
1 Bits

SN74AUP1G80DCKT Applications
There are a lot of Texas Instruments SN74AUP1G80DCKT Flip Flops applications.

Clock pulse
Circuit Design
High Performance Logic for test systems
Instrumentation
Buffered Clock
Bounce elimination switch
Patented noise
Divide a clock signal by 2 or 4
Event Detectors
Computing