Texas Instruments SN74ALVCH374DBRG4
- Part Number:
- SN74ALVCH374DBRG4
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3707795-SN74ALVCH374DBRG4
- Description:
- IC D-TYPE POS TRG SNGL 20SSOP
- Datasheet:
- SN74ALVCH374DBRG4
Texas Instruments SN74ALVCH374DBRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74ALVCH374DBRG4.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case20-SSOP (0.209, 5.30mm Width)
- Number of Pins20
- Operating Temperature-40°C~85°C TA
- PackagingTape & Reel (TR)
- Series74ALVCH
- JESD-609 Codee4
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations20
- Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
- TechnologyCMOS
- Voltage - Supply1.65V~3.6V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Supply Voltage1.8V
- Terminal Pitch0.65mm
- Reflow Temperature-Max (s)NOT SPECIFIED
- Base Part Number74ALVCH374
- FunctionStandard
- Qualification StatusNot Qualified
- Output TypeTri-State, Non-Inverted
- Number of Elements1
- PolarityNon-Inverting
- Supply Voltage-Max (Vsup)3.6V
- Number of Ports2
- Number of Bits8
- Clock Frequency150MHz
- Propagation Delay3.6 ns
- Turn On Delay Time1.1 ns
- FamilyALVC/VCX/A
- Logic FunctionD-Type, Flip-Flop
- Current - Quiescent (Iq)10μA
- Output Characteristics3-STATE
- Current - Output High, Low24mA 24mA
- Max Propagation Delay @ V, Max CL3.6ns @ 3.3V, 50pF
- Trigger TypePositive Edge
- Input Capacitance5pF
- Number of Input Lines8
- Clock Edge Trigger TypePositive Edge
- Height Seated (Max)2mm
- Length7.2mm
- Width5.3mm
- RoHS StatusROHS3 Compliant
SN74ALVCH374DBRG4 Overview
This product is currently obsolete and no longer being produced. It has a terminal finish of Nickel/Palladium/Gold (Ni/Pd/Au) and a voltage supply range of 1.65V to 3.6V. The peak reflow temperature is 260 degrees Celsius. It has one element and two ports. The turn on delay time is 1.1 nanoseconds. The maximum propagation delay at the specified voltage and load capacitance is 3.6 nanoseconds. This product is triggered by a positive edge and has a positive edge clock trigger type.
SN74ALVCH374DBRG4 Features
Tape & Reel (TR) package
74ALVCH series
20 pins
8 Bits
SN74ALVCH374DBRG4 Applications
There are a lot of Texas Instruments SN74ALVCH374DBRG4 Flip Flops applications.
Supports Live Insertion
Common Clocks
Load Control
Differential Individual
CMOS Process
Balanced Propagation Delays
Buffer registers
ESD protection
Computers
Safety Clamp
This product is currently obsolete and no longer being produced. It has a terminal finish of Nickel/Palladium/Gold (Ni/Pd/Au) and a voltage supply range of 1.65V to 3.6V. The peak reflow temperature is 260 degrees Celsius. It has one element and two ports. The turn on delay time is 1.1 nanoseconds. The maximum propagation delay at the specified voltage and load capacitance is 3.6 nanoseconds. This product is triggered by a positive edge and has a positive edge clock trigger type.
SN74ALVCH374DBRG4 Features
Tape & Reel (TR) package
74ALVCH series
20 pins
8 Bits
SN74ALVCH374DBRG4 Applications
There are a lot of Texas Instruments SN74ALVCH374DBRG4 Flip Flops applications.
Supports Live Insertion
Common Clocks
Load Control
Differential Individual
CMOS Process
Balanced Propagation Delays
Buffer registers
ESD protection
Computers
Safety Clamp
SN74ALVCH374DBRG4 More Descriptions
ALVC/VCX/A SERIES 8-BIT DRIVER TRUE OUTPUT PDSO20
IC D-TYPE POS TRG SNGL 20SSOP
Contact for details
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
IC D-TYPE POS TRG SNGL 20SSOP
Contact for details
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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