Texas Instruments SN74ABT3614-20PQ

FIFO Mem Sync Dual Bi-Dir 64 x 36 x 2 132-Pin BQFP
74ABT3614 Tray 8542.32.00.71 74ABT fifo memory 50MHz 130mA 0.635mm 20ns
IC SYNC FIFO MEM 64X36X2 132-QFP
BI-DIRECTIONAL FIFO, 64X36, 12NS
The SN74ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. Two independent 64 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. The SN74ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. The SN74ABT3614 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications (literature number SCAA014) Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications (literature number SCAA015) Internetworking the SN74ABT3614 (literature number SCAA015) Metastability Performance of Clocked FIFOs (literature number SCZA004)