Diodes Incorporated PI6C20400BLE

Description
The P16C20400B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be a companion to a PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specifications.
The device distributes the differential SRC clock from a PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without a PLL. The clock outputs are controlled by input selection of SRC STOP, PWRDWN, and SMBus, SCLK, and SDA. When the input of either SRC STOP or PWRDWN is low, the output clocks are tristated. When PWRDWN# is low, the SDA and SCLK inputs must be tri-stated.

Features
Phase jitter filter for PCIe 3.0 application
Four pairs of differential clocks
Low skew < 50ps
Low jitter < 50ps cycle-to-cycle
< 1 ps additive RMS phase jitter
Output enable for all outputs
Output tristate control via SMBus
Programmable PLL bandwidth
100 MHz PLL mode operation
100-400 MHz bypass mode operation
3.3V operation
Packaging (Pb-free and Green):
28-Pin SSOP (H28)
28-Pin TSSOP (L28)

Applications
PCIe 3.0 clock distribution
Clock buffering for high-speed applications
Clock generation for PCIe 3.0 devices