AT24C02 Pinout, Working Principle, Characteristics and More
19 March 2024
Ⅱ. Working principle of AT24C02
Ⅲ. Pins and functions of AT24C02
Ⅵ. What should we pay attention to when using AT24C02?
Ⅶ. How to realize communication between AT24C02 and microcontroller?
AT24C02 is a serial EEPROM memory produced by Atmel. It uses a 2-wire serial interface, i.e. I2C bus interface, to support multi-host systems, ensuring the flexibility and convenience of data exchange between multiple devices. Its operating voltage range is wide, from 1.8V to 5.5V, allowing it to operate stably in a variety of voltage environments. Due to these excellent characteristics, AT24C02 is widely used in instrumentation, industrial control, consumer electronics and other fields. This article will introduce the AT24C02 in detail to help you better understand and apply this chip.
AT24C02 is a 2K-bit (i.e. 256 bytes) serial EEPROM (Electrically Erasable Programmable Read-Only Memory), which is commonly used for data storage in 51 microcontroller systems. AT24C02 uses the I2C bus protocol to communicate and is connected to the microcontroller through two lines (SCL and SDA). It has an 8-bit device address that can be programmed through pins A0, A1 and A2, thus allowing multiple AT24C02s to coexist on the same I2C bus. For AT24C02, in terms of read and write speed, it supports the standard mode of 400kHz, has a data storage capacity of up to 10 years, and has a write protection function to effectively prevent misoperation. In the microcontroller system, we can use AT24C02 to store various data, such as configuration parameters, calibration data, history records, etc. The microcontroller can call the corresponding I2C library function to write or read data to AT24C02, thereby realizing read and write operations on its storage space. It is worth noting that the AT24C02 is a non-volatile memory that retains stored data even when the power is turned off. Therefore, it is very suitable for application scenarios that require long-term data storage.
The working process of AT24C02 mainly includes four parts, namely writing, reading, erasing and write protection. Here's how it works:
1. Writing: When data needs to be written to AT24C02, it first selects the corresponding I2C address, and then transmits the data to the SDA pin. In this process, the SCL pin is responsible for generating a clock signal and controlling the rate and timing of data transmission. Finally, through these steps, it can complete the data writing operation.
2. Reading: When data needs to be read from AT24C02, it also needs to select the corresponding I2C address and send a read command, and then the SCL pin generates a clock signal to read the data on the SDA pin.
3. Erase: When you need to write data to AT24C02, first select the corresponding I2C address, and then transfer the data to the SDA pin. In this process, the SCL pin is responsible for generating a clock signal and controlling the rate and timing of data transmission. Finally, through these steps, AT24C02 can complete the data writing operation.
4. Write protection: In order to ensure the security and reliability of data, AT24C02 also provides a write protection function, which controls whether the chip can be written through the WP pin. When the WP pin is connected to ground, the chip is in a writable state. When the WP pin is left floating or connected to VCC, the chip is in a read-only state.
The pins of AT24C02 are shown in the figure above, and the functions of each pin are as follows:
• SCL: This is the serial clock input pin used to generate the clock for all data transmission or reception by the device.
• SDA: This is the bidirectional serial data or address pin used to send or receive all data to the device.
• A0, A1, A2: These are the address inputs of the device and are used to set the address of each device when multiple devices are cascaded. When these pins are left floating, their default value is 0. When using AT24C02, up to 8 devices can be cascaded on an I2C bus. If only one AT24C02 is addressed on the bus, then the three address input pins A0, A1, and A2 can be left floating or connected to VSS (power ground).
• WP: This is write protected. If the WP pin is connected to Vcc, all contents are write protected and can only be read. When the WP pin is connected to Vss or left floating, the device is allowed to perform normal read or write operations.
• VSS: This is the power ground (GND).
• VCC: This is the supply voltage (5V).
1. Basic structure of I2C bus
A microcontroller or I2C device that adopts the I2C bus standard not only integrates the I2C interface circuit, but also divides the internal unit circuits into multiple relatively independent modules according to their functions. These modules implement chip select through software addressing, thereby reducing the number of device chip select line connections. The CPU can not only connect or disconnect a functional unit circuit to the bus through instructions, but can also detect the working status of the unit. This design makes the expansion and control of the hardware system simple and flexible.
2. Interface characteristics of two-way transmission
Traditional microcontroller serial interfaces usually use two lines for sending and receiving data respectively, while the I2C bus configures the device functions through a software program so that it can work in sending or receiving mode. When a device sends data on the bus, it acts as a transmitter (i.e., a master), and when it receives data from the bus, it becomes a receiver (i.e., a slave). The master device is responsible for initiating data transmission on the bus and generating clock signals to control the data transmission process. At this time, any addressed device participates in data transmission as a slave device. The control of the I2C bus depends entirely on the address and data sent by the master device attached to the bus.
The relationship between the master device and the slave device (i.e. transmitter and receiver) on the bus is not fixed, but depends on the current direction of data transmission. SDA and SCL are bidirectional I/O lines that are connected to the positive supply through pull-up resistors. When the bus is idle, both lines remain high. The output stages of devices connected to the bus must be of the open-collector or drain type in order to implement the wired AND function. In the standard working mode, the data transfer rate of the I2C bus is 100kbit/s; in the fast mode, the maximum transfer rate can reach 400kbit/s.
3. Clock signal on the I2C bus
The clock synchronization signal when transmitting information on the I2C bus is completed by the logical AND of all devices connected to the SCL clock line. The transition from high level to low level on the SCL line will affect these devices. Once the clock signal of a certain device jumps to low level, the SCL line will remain low level, causing all the signals on the SCL line to remain low. The device begins a low period. At this time, the low-to-high clock transition of devices with short low-level periods cannot affect the state of the SCL line, so these devices will enter a high-level waiting state.
When the clock signals of all devices jump to high level, the low level period ends and the SCL line is released back to high level, that is, all devices start their high level period at the same time. Thereafter, the first device to end the high period pulls the SCL line low again. This generates a synchronization clock on the SCL line. It can be seen that the clock low time is determined by the device with the longest clock low period, and the clock high time is determined by the device with the shortest clock high period.
4. Data transmission
During the data transfer process, we must clearly define the start and end times of data transfer. When the clock line SCL is in a high level state, the data line SDA jumps from high level to low level, which is defined as the "start" signal; similarly, when the SCL line remains high level, the SDA line changes from low level to low level. A flat transition to high level is defined as the "end" signal. These start and end signals are generated by the master device. After the start signal is sent, the bus enters the busy state; within a period of time after the end signal is sent, the bus is in the idle state.
The data transmission format of the I2C bus is as follows: after the I2C bus sends the start signal, the first byte of data sent immediately is used to select the slave device address. Among them, the first 7 bits are the address code, used to identify a specific slave device; and the 8th bit is the direction bit (R/W), used to indicate the direction of data transmission. When the direction bit is "0", it indicates a sending operation, that is, the master device writes information to the selected slave device; when the direction bit is "1", it indicates a receiving operation, that is, the master device writes information from the selected slave device Read information from the device. After sending the start signal, each device in the system compares its address with the address sent by the master device on the bus. If the addresses are consistent, the device is addressed by the master device, and whether to receive information or send information is determined based on the value of bit 8 (R/W).
On the I2C bus, there is no limit to the number of data bytes that can be transmitted at a time, but each byte must be strictly 8 bits. And, each transmitted byte must be followed by an acknowledgement bit (also known as an answer bit, or ACK) as an acknowledgement of data reception. When transmitting data, the highest bit is always transmitted first. Normally, the slave device responds to each byte received by releasing the SCL line to return it to a high state, ready to receive the next data byte, at which point the master device can continue to transmit data. However, if the slave device is processing a real-time event and is unable to receive data (e.g., it is processing an internal interrupt and is unable to receive a data byte on the I2C bus until the interrupt processing is complete), it can keep the clocked SCL line in a low state. In this case, the slave device must ensure that the SDA line remains high. Once the master device detects this condition, it generates an end signal that ends the data transfer abnormally and forces the master device into a wait state. When the slave device has processed the current event and is ready to continue receiving data, it releases the SCL line, at which point the master device can continue to transmit the remaining data.
When the master device completes sending one byte of data, it will then send out a clock pulse corresponding to the SCL line as the acknowledge bit (ACK). During this clock cycle, the master device releases the SDA line to complete the transfer of one byte. At the same time, the slave device's response signal will pull the SDA line low, ensuring that the SDA line remains stable low while the SCL line is high. After the response signal from the slave device ends, the SDA line will return to the high level state, marking the end of the current transmission cycle and preparing to enter the next transmission cycle.
When using the AT24C02, we need to pay attention to the following points:
• First, we need to pay attention to the storage capacity and addressing method of AT24C02 to ensure correct access and manipulation of data.
• Second, we need to ensure the stability and reliability of the I2C bus to avoid communication interruptions or data errors.
• When performing read operations, we need to ensure that we receive data correctly and handle possible errors or abnormalities.
• When performing write operations, we need to wait for the write to complete before performing the next operation to avoid data conflicts or overwrites.
• When designing circuits and wiring, we need to be careful to avoid problems such as electromagnetic interference and electrostatic discharge to ensure the normal operation and stability of the AT24C02.
The storage capacity of AT24C02 is 2K bit, and its content is divided into 32 pages, each page contains 8Byte, totaling 256Byte. During operation, the device supports two addressing modes, chip addressing and on-chip subaddress addressing.
1. Chip addressing: The chip address of AT24C02 is fixed at 1010, and its address control word format is 1010A2A1A0R/W. Among them, A2, A1, and A0 are programmable address selection bits. They form a specific three-digit code by connecting high level or low level. This three-digit code is combined with the fixed 1010 to form a 7-bit device address code. The A0, A1, and A2 pins are responsible for the address input of the device. When multiple AT24C02 devices need to be cascaded, we can assign different addresses to each device by setting the status of these pins. If these pins are left floating, their default value is usually 0. By changing the pin status of A2, A1, and A0, 8 different address combinations can be obtained, which means that an I2C bus can cascade up to 8 such devices. The R/W bit is the read and write control bit of the chip. When this bit is 0, it means that the chip is performing a write operation. In the following analysis and procedures, we assume that there is only one AT24C02 device, and the A2, A1, and A0 pins are all floating, so their values are all 0. In this way, the address control word becomes 1010000*, where * represents the R/W bit.
In the context of the Blue Bridge Cup competition, if the A0, A1, and A2 pins are all connected to ground, their values will also be 0. Therefore, the entire address control word is 1010000, which is 0xA0 when converted to hexadecimal. Therefore, when programming, we can use 0xA0 as the address of AT24C02.
2. On-chip subaddress addressing: Chip addressing can read or write any byte among the internal 256 bytes. Its addressing range is from 00 to FF, containing a total of 256 addressing units. For example, address 0x80 is one of the valid addressing units.
Frequently Asked Questions
1. What is AT24C02?
AT24C02 is a popular serial EEPROM (Electrically Erasable Programmable Read-Only Memory) chip manufactured by Microchip Technology. It belongs to the AT24Cxx series of EEPROMs.
2. What is the capacity of 24c02?
The device has a page write capability for up to 16 bytes of data and has fast write cycle times of only 1ms for both byte and page writes. Functional address lines allow the connection of up to eight 24C02C devices on the same bus for up to 16kB of contiguous EEPROM memory.
3. How does AT24C02 implement write protection?
AT24C02 provides hardware-based write protection by using a write-protect pin (WP). When this pin is connected to VCC (or set to a logic high level), write operations to the EEPROM are disabled, protecting the stored data from being overwritten.
