ON Semiconductor NB4N111KMNG

Description
The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultralow propagation delay variation. It is designed for HCSL clock distribution in FBDIMM applications. Inputs can accept differential LVPECL, CML, or LVDS levels. Singleended LVPECL, CML, LVCMOS, or LVTTL levels are accepted with the proper VREFAC supply. Clock input pins incorporate an internal 50 Ω ondie termination resistors. Outputs can interface with LVDS with proper termination. The NB4N111K specifically guarantees low outputtooutput skews. Optimal design, layout, and processing minimize skew within a device and from device to device.

Features
Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and 400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Atpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
<1 ps RMS Additive Clock Jitter
Operating Range: Vcc = 3.0 V to 3.6 V with VEE = 0
Differential HCSL Output Level or LVDS with Proper Termination
PbFree Devices

Applications
FBDIMM Clock Distribution
Backplane Clock Distribution
Motherboard Clock Distribution