ON Semiconductor NB3L83948CFAR2G

Description
The NB3L83948C is a clock distribution buffer that can operate in either pure 2.5 V/3.3 V (VDD = VDDO) mode or mixedmode 3.3 V Core (VDD) / 2.5 V Output (VDDO) mode. It can select either a differential LVPECL/LVDS/LVHSTL/SSTL/HCSL or singleended LVCMOS/LVTTL compatible input clock. All other control inputs (CLK SEL, CLK_EN, and OE) are LVTTL/LVCMOS level compatible.
The NB3L83948C has an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs when in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated.
The 12 LVCMOS output pins can drive 50 Ω series or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tristated) via the OE input, or enabled when High.

Features
2.5 V/3.3 V (VDD = VDDO) or 3.3 V VDD/2.5 V VDDO Operation
350 MHz Clock Support
Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS Clock Inputs
LVCMOS Compatible Control Inputs
12 LVCMOS Clock Outputs
Synchronous Clock Select
Output Enable to High Z State Control
100 ps Max. Skew Between Outputs
Industrial Temp. Range 40°C to 85°C
32pin LQFP Package

Applications
Clock Distribution
Clock Buffering
Clock Multiplexing
Clock Fanout