MC100E131FNG

ON Semiconductor MC100E131FNG

Part Number:
MC100E131FNG
Manufacturer:
ON Semiconductor
Ventron No:
3211682-MC100E131FNG
Description:
IC D-TYPE POS TRG SNGL 28PLCC
ECAD Model:
Datasheet:
MC100E131FNG

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Specifications
ON Semiconductor MC100E131FNG technical specifications, attributes, parameters and parts with similar specifications to ON Semiconductor MC100E131FNG.
  • Factory Lead Time
    4 Weeks
  • Lifecycle Status
    ACTIVE (Last Updated: 1 week ago)
  • Mount
    Surface Mount
  • Mounting Type
    Surface Mount
  • Package / Case
    28-LCC (J-Lead)
  • Number of Pins
    28
  • Operating Temperature
    0°C~85°C TA
  • Packaging
    Tube
  • Published
    2006
  • Series
    100E
  • JESD-609 Code
    e3
  • Pbfree Code
    yes
  • Part Status
    Active
  • Moisture Sensitivity Level (MSL)
    3 (168 Hours)
  • Number of Terminations
    28
  • Terminal Finish
    Tin (Sn)
  • Subcategory
    FF/Latches
  • Technology
    ECL
  • Voltage - Supply
    -4.2V~-5.7V
  • Terminal Position
    QUAD
  • Terminal Form
    J BEND
  • Peak Reflow Temperature (Cel)
    260
  • Supply Voltage
    5V
  • Reflow Temperature-Max (s)
    40
  • Base Part Number
    100E131
  • Function
    Set(Preset) and Reset
  • Output Type
    Differential
  • Number of Elements
    1
  • Polarity
    Non-Inverting
  • Supply Voltage-Max (Vsup)
    5.7V
  • Output Current
    50mA
  • Number of Bits
    4
  • Clock Frequency
    1.4GHz
  • Propagation Delay
    675 ps
  • Turn On Delay Time
    500 ps
  • Logic Function
    D-Type, Flip-Flop
  • Current - Quiescent (Iq)
    70mA
  • Output Characteristics
    OPEN-EMITTER
  • Halogen Free
    Halogen Free
  • Trigger Type
    Positive Edge
  • High Level Output Current
    50mA
  • Low Level Output Current
    50mA
  • Number of Input Lines
    4
  • Clock Edge Trigger Type
    Positive Edge
  • Radiation Hardening
    No
  • RoHS Status
    ROHS3 Compliant
  • Lead Free
    Lead Free
Description
MC100E131FNG Overview
The package is in the form of 28-LCC (J-Lead). As part of the package Tube, it is embedded. It is configured with Differentialas an output. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis occupied by this electronic component. The JK flip flop operates with an input voltage of -4.2V~-5.7V volts. 0°C~85°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. The FPGA belongs to the 100E series. A frequency of 1.4GHzshould not be exceeded by its output. The element count is 1 . There is a consumption of 70mAof quiescent energy. It has been determined that there have been 28 terminations. The object belongs to the 100E131 family. A voltage of 5V is used as the power supply for this D latch. There is an electronic part that is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 28. Its clock edge trigger type is Positive Edge. This part is included in FF/Latches. There are 4bits in this flip flop. It reaches the maximum supply voltage (Vsup) at 5.7V. Its output current of 50mAallows for maximum design flexibility. It is reported that there are 4 input lines. It is set to 50mAfor the high level output current. 50mA is the low level output current.

MC100E131FNG Features
Tube package
100E series
28 pins
4 Bits

MC100E131FNG Applications
There are a lot of ON Semiconductor MC100E131FNG Flip Flops applications.

Modulo – n – counter
Bounce elimination switch
Differential Individual
Computers
Pattern generators
Data Synchronizers
Safety Clamp
Asynchronous counter
ESD performance
2 – Bit synchronous counter
MC100E131FNG More Descriptions
Flip Flop D-Primary-Secondary Type Pos-Edge 1-Element 28-Pin PLCC Rail
D-Type Flip Flop Quad, 0.5Ns Plcc-28; Logic Family/Base Number:-; Flip-Flop Type:D; Propagation Delay:500Ps; Frequency:1.4Ghz; Output Current:50Ma; Logic Case Style:Lcc; No. Of Pins:28Pins; Trigger Type:Positive Edge Rohs Compliant: Yes |Onsemi MC100E131FNG
The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using CC to clock all four flip-flops. In this case the CEbar inputs perform the function of controlling the common clock to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CEbar are LOW and transfers to the slave when either CC or CEbar (or both) go HIGH. The 100 Series contains temperature compensation.
Certification
  • ISO 9001
  • ISO 13485
  • ISO 45001
  • ASA
  • ESD
  • DUNS
  • SMTA
  • ROHS

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