Altera EP2S30F672C3
- Part Number:
- EP2S30F672C3
- Manufacturer:
- Altera
- Ventron No:
- 3130650-EP2S30F672C3
- Description:
- IC FPGA 500 I/O 672FBGA
- ECAD Model:
-
- Datasheet:
- Stratix II Device Handbook
Altera EP2S30F672C3 technical specifications, attributes, parameters and parts with similar specifications to Altera EP2S30F672C3.
- Mounting TypeSurface Mount
- Package / Case672-BBGA, FCBGA
- Surface MountYES
- Operating Temperature0°C~85°C TJ
- PackagingTray
- SeriesStratix® II
- JESD-609 Codee0
- Part StatusNot For New Designs
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations672
- ECCN Code3A001.A.7.A
- Terminal FinishTIN LEAD
- HTS Code8542.39.00.01
- SubcategoryField Programmable Gate Arrays
- TechnologyCMOS
- Voltage - Supply1.15V~1.25V
- Terminal PositionBOTTOM
- Terminal FormBALL
- Peak Reflow Temperature (Cel)220
- Supply Voltage1.2V
- Terminal Pitch1.27mm
- Reflow Temperature-Max (s)30
- Base Part NumberEP2S30
- JESD-30 CodeS-PBGA-B672
- Number of Outputs492
- Qualification StatusNot Qualified
- Power Supplies1.21.5/3.33.3V
- Number of I/O500
- Clock Frequency717MHz
- Number of Inputs500
- Organization13552 CLBS
- Programmable Logic TypeFIELD PROGRAMMABLE GATE ARRAY
- Number of Logic Elements/Cells33880
- Total RAM Bits1369728
- Number of LABs/CLBs1694
- Combinatorial Delay of a CLB-Max4.45 ns
- Number of CLBs13552
- Height Seated (Max)2.6mm
- Length35mm
- Width35mm
- RoHS StatusNon-RoHS Compliant
EP2S30F672C3 Overview
The Altera chip belongs to the Embedded - FPGAs category and is produced by Altera. Its technology is CMOS, with a TIN LEAD terminal finish. The peak reflow temperature is 220 degrees Celsius and it has not yet been qualified. The clock frequency is 717MHz and it has 33880 logic elements/cells. The combinatorial delay of a CLB-Max is 4.45 ns and it has 13552 CLBs. The length of the chip is 35mm and it is currently not RoHS compliant.
EP2S30F672C3 Features
500 I/Os
Up to 1369728 RAM bits
EP2S30F672C3 Applications
There are a lot of Intel EP2S30F672C3 FPGAs applications.
Camera time adjustments
ADAS
Data center search engines
Consumer Electronics
Telecommunication
Artificial intelligence (AI)
Software-defined radio
Cryptography
Enterprise networking
Random logic
The Altera chip belongs to the Embedded - FPGAs category and is produced by Altera. Its technology is CMOS, with a TIN LEAD terminal finish. The peak reflow temperature is 220 degrees Celsius and it has not yet been qualified. The clock frequency is 717MHz and it has 33880 logic elements/cells. The combinatorial delay of a CLB-Max is 4.45 ns and it has 13552 CLBs. The length of the chip is 35mm and it is currently not RoHS compliant.
EP2S30F672C3 Features
500 I/Os
Up to 1369728 RAM bits
EP2S30F672C3 Applications
There are a lot of Intel EP2S30F672C3 FPGAs applications.
Camera time adjustments
ADAS
Data center search engines
Consumer Electronics
Telecommunication
Artificial intelligence (AI)
Software-defined radio
Cryptography
Enterprise networking
Random logic
EP2S30F672C3 More Descriptions
FPGA Stratix® II Family 33880 Cells 816.99MHz 90nm Technology 1.2V 672-Pin FC-FBGA
Field Programmable Gate Array, 13552 CLBs, 717MHz, 33880-Cell, CMOS, PBGA672
Contains Lead CMOS OTHER 2007 FPGA 85C 300mA 167.2kB 4.45ns
IC FPGA 500 I/O 672FBGA Stratix II
SWITCH SNAP ACT SPST-NO 16A 250V
Field Programmable Gate Array, 13552 CLBs, 717MHz, 33880-Cell, CMOS, PBGA672
Contains Lead CMOS OTHER 2007 FPGA 85C 300mA 167.2kB 4.45ns
IC FPGA 500 I/O 672FBGA Stratix II
SWITCH SNAP ACT SPST-NO 16A 250V
The three parts on the right have similar specifications to EP2S30F672C3.
-
ImagePart NumberManufacturerMounting TypePackage / CaseSurface MountOperating TemperaturePackagingSeriesJESD-609 CodePart StatusMoisture Sensitivity Level (MSL)Number of TerminationsECCN CodeTerminal FinishHTS CodeSubcategoryTechnologyVoltage - SupplyTerminal PositionTerminal FormPeak Reflow Temperature (Cel)Supply VoltageTerminal PitchReflow Temperature-Max (s)Base Part NumberJESD-30 CodeNumber of OutputsQualification StatusPower SuppliesNumber of I/OClock FrequencyNumber of InputsOrganizationProgrammable Logic TypeNumber of Logic Elements/CellsTotal RAM BitsNumber of LABs/CLBsCombinatorial Delay of a CLB-MaxNumber of CLBsHeight Seated (Max)LengthWidthRoHS StatusFactory Lead TimeView Compare
-
EP2S30F672C3Surface Mount672-BBGA, FCBGAYES0°C~85°C TJTrayStratix® IIe0Not For New Designs3 (168 Hours)6723A001.A.7.ATIN LEAD8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2201.2V1.27mm30EP2S30S-PBGA-B672492Not Qualified1.21.5/3.33.3V500717MHz50013552 CLBSFIELD PROGRAMMABLE GATE ARRAY33880136972816944.45 ns135522.6mm35mm35mmNon-RoHS Compliant-- -
Surface Mount1020-BBGAYES0°C~85°C TJTrayStratix® IIe1Active3 (168 Hours)-3A001.A.7.ATin/Silver/Copper (Sn/Ag/Cu)8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2451.2V1mm40EP2S180S-PBGA-B1020734Not Qualified1.21.5/3.33.3V742640MHz74271760 CLBSFIELD PROGRAMMABLE GATE ARRAY179400938304089705.962 ns717603.5mm33mm33mmRoHS Compliant8 Weeks
-
Surface Mount1020-BBGAYES0°C~85°C TJTrayStratix® IIe1Active3 (168 Hours)-3A001.A.7.ATin/Silver/Copper (Sn/Ag/Cu)8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2451.2V1mm40EP2S130S-PBGA-B1020734Not Qualified1.21.5/3.33.3V742717MHz742-FIELD PROGRAMMABLE GATE ARRAY132540674784066274.672 ns-3.5mm33mm33mmRoHS Compliant8 Weeks
-
Surface Mount672-BBGA, FCBGAYES0°C~85°C TJTrayStratix® IIe0Not For New Designs3 (168 Hours)6723A991TIN LEAD8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2201.2V1.27mm30EP2S15S-PBGA-B672358Not Qualified1.21.5/3.33.3V366717MHz3666240 CLBSFIELD PROGRAMMABLE GATE ARRAY156004193287805.117 ns62402.6mm35mm35mmNon-RoHS Compliant-
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