All You Need to Know the CD4013 CMOS Dual D Flip Flop
29 November 2023
Ⅲ. Pin configuration of CD4013
Ⅳ. What are the features of CD4013?
Ⅵ. What are the applications of CD4013?
Ⅶ. CD4013 switch application circuit
The CD4013 flip-flop has a wide range of applications in digital circuits and can be used to implement various types of digital logic circuits to achieve various functions. In this article, we will introduce the features and working principle of CD4013, so that you can better understand and apply the chip.
D flip-flop is an electronic component that constitutes a variety of timing circuits of the most basic logic unit, but also an important unit circuit in the digital logic circuit. Its principle is based on the composition of two complementary flip-flops, one of which is the RS flip-flop, the other for the JK flip-flop. D flip-flop can be synchronized with the input clock signal and input data signal, and in the clock signal edge changes in the data signal will be written to the flip-flop.
The CD4013 is a CMOS digital integrated circuit with high impedance inputs and outputs that can operate over a wide range of voltage and temperature conditions. Its operating voltage range is from 3V to 18V, while its operating temperature range is from -55°C to 125°C. The CD4013 is designed to operate over a wide range of voltages and temperatures.
The CD4013 is a device consisting of two identical, mutually independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. It can be used either as a shift register, by connecting the Q output to the data input, or as a calculator and flip-flop. When triggered on the rising edge of the clock, a logic level applied to the D input is transmitted to the Q output. Setting and resetting are not related to the clock but are accomplished by a high level on the set or reset line, respectively.
Replacements and equivalents:
• C073
• MC14013
• NTE4013
• TC4013
• 74HC74
It has a total of 14 pins, their names and descriptions are as follows.
Pin 1 (Q1): The output of D flip flop 1
Pin 2 (Q1'): The inverted output of D flip flop 1
Pin 3 (CLK 1): Clock pin 1
Pin 4 (RESET 1): Reset pin 1
Pin 5 (D1): Data pin 1
Pin 6 (SET 1): Set pin 1
Pin 7 (VSS): Supply voltage
Pin 8 (SET 2): Set pin 2
Pin 9 (D2): Data pin 2
Pin 10 (RESET 2): Reset pin 2
Pin 11 (CLK 2): Clock pin 2
Pin 12 (Q2'): The inverted output of D flip flop 2
Pin 13 (Q2): The output of D flip flop 2
Pin 14 (VDD): Drain voltage
• The pin arrangement of the CD4013 is designed to be very compact in order to accommodate two flip-flops and other logic circuits in a limited space.
• It has a relatively large output current capability, enabling it to drive a certain load.
• Each D flip-flop has a clock input for triggering the flip-flop on the rising or falling edge of the clock signal.
• The inputs have a high input impedance, which helps minimize the effect of external circuitry on the performance of the CD4013.
• The CD4013 utilizes CMOS technology, which makes it low-power and suitable for use in battery-powered applications.
We set the initial state of the circuit are in the reset state, Q1, Q2 terminal are low. When the fi signal is input, its output is controlled by the feedback from the Q2 end of the flip-flop IC2 due to the logic function of the hetero-or gate at the input. Under the action of the rising edge of the 1st fi clock pulse, both flip-flops of flip-flops IC1 and IC2 occur. Due to the feedback at the Q2 end, the heterodyne gate outputs a very narrow positive pulse whose width is determined by the delay of the two-stage D flip-flop and the inverting gate. When the 1st fi pulse jumps down, the heterodyne gate output jumps up again immediately, causing IC1 flip-flop to flip-flop again. And for half a cycle of the 1st input clock, the clock pulse terminal CL1 of the IC1 flip-flop receives a full cycle of the input signal. With a later input clock, the Q2 terminal of the IC2 flip-flop stays high, and the clock input of the IC1 flip-flop will follow the fi signal (or be inverted or in-phase). Originally, the IC1 flip-flop needs two complete input pulses to output a pulse of one complete cycle. However, due to the feedback control effect of the heterodyne gate and the Q2 end of the IC2 flip-flop, it realizes that for every one and a half clock pulse input, it obtains a full cycle output at the Q1 end of the IC1 flip-flop.
• State machine: In digital systems, CD4013 can be used to construct state machines for realizing specific state transitions and control logic.
• Flip-flop: As an integrated circuit of D flip-flop, CD4013 can be used to construct various flip-flop circuits, such as JK flip-flop and RS flip-flop. These circuits can be used to store information and can realize timing logic and control the state of the circuit.
• Digital signal processing: It can be used to synchronize and control data flow in some digital signal processing applications.
• Frequency divider: The CD4013 is suitable for creating frequency dividers, allowing the reduction of the input signal frequency to the desired level through proper configuration of the clock input and flip-flop connections.
• Pulse generator: We can build a pulse generator by utilizing the features of CD4013 to generate pulse signals with specific timing.
• Timing logic: It can be used to design various timing logic circuits such as frequency dividers and counters. By connecting multiple CD4013s, it is possible to build more complex counting and timing circuits.
• Data storage: In addition to this, the CD4013 can be used as a data storage element. Data can be written to the CD4013 using the appropriate clock and data input signals and can be read when needed.
The power switching circuit is composed of a double D trigger CD4013 and a resistor. As shown in the figure, IC (a) and R1, C form a monostable trigger. (Monostable circuits are characterized by only one stable state, and will return to the original stable state after a period of time after the trigger is flipped.) IC(b), on the other hand, constitutes a bistable flip-flop (A bistable circuit has two stable states that will remain after the trigger flip-flop and has a memory effect. It is often used as a memory or counter).
CP is the pulse input, R is the reset, S is the set, and Q is the output. When M is pressed, CP1 rising edge comes. Since D1 is always 1, Q1 is high, and at this time Q1 charges C1 through R1. When the voltage on C1 reaches the level of the trigger reset terminal, Q1 changes from high to low, with a transition time of about 0.7R1*C. Since Q1 is connected to CP2, a pulse is generated at CP2. Since D is not connected to Q, Q flips once for each pulse generated, realizing the function of the switch.
Frequently Asked Questions
1. What is the use of CD4013?
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications.
2. What is the equivalent of CD4013?
You likely find the 4013 IC marked as CD4013, NTE4013, MC14013, HCF4013, TC4013, or HEF4013. Usually with a few extra characters at the end (Ex: CD4013BE). This has to do with the manufacturer of the chip and the technology used. But the functionality and the pins are the same.
3. How does CD4013 work?
The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications.
4. What is IC 4013 function?
The 4013 contains two independent D-type flip-flops with asynchronous set/reset inputs. Whenever the set or reset pins go high, the appropriate output is expressed immediately on the outputs. When set and reset are low, the output shows the data at the input at the time of the last low-to-high clock transition.
