Altera EP2S15F672C5
- Part Number:
- EP2S15F672C5
- Manufacturer:
- Altera
- Ventron No:
- 3637293-EP2S15F672C5
- Description:
- IC FPGA 366 I/O 672FBGA
- Datasheet:
- Stratix II Device Handbook
Altera EP2S15F672C5 technical specifications, attributes, parameters and parts with similar specifications to Altera EP2S15F672C5.
- Mounting TypeSurface Mount
- Package / Case672-BBGA, FCBGA
- Surface MountYES
- Operating Temperature0°C~85°C TJ
- PackagingTray
- SeriesStratix® II
- JESD-609 Codee0
- Part StatusNot For New Designs
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations672
- ECCN Code3A991
- Terminal FinishTIN LEAD
- HTS Code8542.39.00.01
- SubcategoryField Programmable Gate Arrays
- TechnologyCMOS
- Voltage - Supply1.15V~1.25V
- Terminal PositionBOTTOM
- Terminal FormBALL
- Peak Reflow Temperature (Cel)220
- Supply Voltage1.2V
- Terminal Pitch1.27mm
- Reflow Temperature-Max (s)30
- Base Part NumberEP2S15
- JESD-30 CodeS-PBGA-B672
- Number of Outputs358
- Qualification StatusNot Qualified
- Power Supplies1.21.5/3.33.3V
- Number of I/O366
- Clock Frequency640MHz
- Number of Inputs366
- Organization6240 CLBS
- Programmable Logic TypeFIELD PROGRAMMABLE GATE ARRAY
- Number of Logic Elements/Cells15600
- Total RAM Bits419328
- Number of LABs/CLBs780
- Combinatorial Delay of a CLB-Max5.962 ns
- Number of CLBs6240
- Height Seated (Max)2.6mm
- Length35mm
- Width35mm
- RoHS StatusNon-RoHS Compliant
EP2S15F672C5 Overview
The JESD-609 Code for this particular component is e0, indicating its classification as Not For New Designs. This means that it is not recommended for use in new products or designs. The component has a total of 672 terminations, with the terminal position located at the bottom. The peak reflow temperature for this component is 220 degrees Celsius. The supply voltage required for this component is 1.2V. The JESD-30 Code for this component is S-PBGA-B672, indicating its specific package type. It has a total of 366 input/output pins. Additionally, the component has a total of 419,328 bits of RAM. The maximum seated height for this component is 2.6mm.
EP2S15F672C5 Features
366 I/Os
Up to 419328 RAM bits
EP2S15F672C5 Applications
There are a lot of Intel EP2S15F672C5 FPGAs applications.
Random logic
Cryptography
Distributed Monetary Systems
Ecosystem
Scientific Instruments
Medical ultrasounds
Data center hardware accelerators
ASIC prototyping
Data Center
Software-defined radios
The JESD-609 Code for this particular component is e0, indicating its classification as Not For New Designs. This means that it is not recommended for use in new products or designs. The component has a total of 672 terminations, with the terminal position located at the bottom. The peak reflow temperature for this component is 220 degrees Celsius. The supply voltage required for this component is 1.2V. The JESD-30 Code for this component is S-PBGA-B672, indicating its specific package type. It has a total of 366 input/output pins. Additionally, the component has a total of 419,328 bits of RAM. The maximum seated height for this component is 2.6mm.
EP2S15F672C5 Features
366 I/Os
Up to 419328 RAM bits
EP2S15F672C5 Applications
There are a lot of Intel EP2S15F672C5 FPGAs applications.
Random logic
Cryptography
Distributed Monetary Systems
Ecosystem
Scientific Instruments
Medical ultrasounds
Data center hardware accelerators
ASIC prototyping
Data Center
Software-defined radios
EP2S15F672C5 More Descriptions
FPGA Stratix II Family 15600 Cells 609.76MHz 90nm (CMOS) Technology 1.2V 672-Pin FC-FBGA
Field Programmable Gate Array, 6240 CLBs, 640MHz, 15600-Cell, CMOS, PBGA672
IC FPGA 366 I/O 672FBGA Stratix II
French Electronic Distributor since 1988
Field Programmable Gate Array, 6240 CLBs, 640MHz, 15600-Cell, CMOS, PBGA672
IC FPGA 366 I/O 672FBGA Stratix II
French Electronic Distributor since 1988
The three parts on the right have similar specifications to EP2S15F672C5.
-
ImagePart NumberManufacturerMounting TypePackage / CaseSurface MountOperating TemperaturePackagingSeriesJESD-609 CodePart StatusMoisture Sensitivity Level (MSL)Number of TerminationsECCN CodeTerminal FinishHTS CodeSubcategoryTechnologyVoltage - SupplyTerminal PositionTerminal FormPeak Reflow Temperature (Cel)Supply VoltageTerminal PitchReflow Temperature-Max (s)Base Part NumberJESD-30 CodeNumber of OutputsQualification StatusPower SuppliesNumber of I/OClock FrequencyNumber of InputsOrganizationProgrammable Logic TypeNumber of Logic Elements/CellsTotal RAM BitsNumber of LABs/CLBsCombinatorial Delay of a CLB-MaxNumber of CLBsHeight Seated (Max)LengthWidthRoHS StatusFactory Lead TimeView Compare
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EP2S15F672C5Surface Mount672-BBGA, FCBGAYES0°C~85°C TJTrayStratix® IIe0Not For New Designs3 (168 Hours)6723A991TIN LEAD8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2201.2V1.27mm30EP2S15S-PBGA-B672358Not Qualified1.21.5/3.33.3V366640MHz3666240 CLBSFIELD PROGRAMMABLE GATE ARRAY156004193287805.962 ns62402.6mm35mm35mmNon-RoHS Compliant--
-
Surface Mount780-BBGAYES0°C~85°C TJTrayStratix® IIe1Active3 (168 Hours)7803A001.A.7.ATin/Silver/Copper (Sn/Ag/Cu)8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2451.2V1mm40EP2S130S-PBGA-B780526Not Qualified1.21.5/3.33.3V534640MHz534-FIELD PROGRAMMABLE GATE ARRAY132540674784066275.962 ns-3.5mm29mm29mmRoHS Compliant8 Weeks
-
Surface Mount484-BBGAYES0°C~85°C TJTrayStratix® IIe1Active3 (168 Hours)4843A991Tin/Silver/Copper (Sn/Ag/Cu)8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2601.2V1mm40EP2S15S-PBGA-B484334Not Qualified1.21.5/3.33.3V342717MHz3426240 CLBSFIELD PROGRAMMABLE GATE ARRAY156004193287805.117 ns62403.5mm23mm23mmRoHS Compliant8 Weeks
-
Surface Mount1020-BBGAYES0°C~85°C TJTrayStratix® IIe0Not For New Designs3 (168 Hours)-3A001.A.7.ATIN LEAD8542.39.00.01Field Programmable Gate ArraysCMOS1.15V~1.25VBOTTOMBALL2201.2V1mm30EP2S180S-PBGA-B1020734Not Qualified1.21.5/3.33.3V742717MHz74271760 CLBSFIELD PROGRAMMABLE GATE ARRAY179400938304089704.672 ns717603.5mm33mm33mmNon-RoHS Compliant-
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