Cypress Semiconductor Corp CY2DL1504ZXC

Description
The CY2DL1504 is a differential LVDS fanout buffer with selectable clock input. It can select between two differential input pairs (LVPECL, LVDS, HCSL, or CML) and distribute them to four LVDS output pairs. The device translates any singleended input signal to 3.3 V LVDS levels with resistor bias on the INx# input. It has a maximum outputtooutput skew of 30 ps, a maximum propagation delay of 480 ps, and a maximum additive RMS phase jitter of 0.11 ps at 156.25 MHz (12 kHz to 20 MHz offset). The CY2DL1504 operates at up to 1.5 GHz and has output enable and synchronous clock enable functions. It is available in a 20pin TSSOP package and operates at 2.5 V or 3.3 V. The device has a commercial and industrial operating temperature range.

Features
Selectable differential input pairs (LVPECL, LVDS, HCSL, or CML)
Translates singleended input signals to 3.3 V LVDS levels
Maximum outputtooutput skew of 30 ps
Maximum propagation delay of 480 ps
Maximum additive RMS phase jitter of 0.11 ps at 156.25 MHz (12 kHz to 20 MHz offset)
Up to 1.5 GHz operation
Output enable and synchronous clock enable functions
20pin TSSOP package
2.5 V or 3.3 V operating voltage
Commercial and industrial operating temperature range

Applications
Highspeed clock distribution
Data communication
Networking
Test and measurement