Cypress Semiconductor Corp CY2305SXC-1H

Description
The CY2305/CY2309 is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks. It accepts one reference input and drives out multiple low skew clocks. The CY2305 has five outputs, while the CY2309 has nine outputs, grouped as 4 4 1. Both devices have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can be controlled by the select inputs. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.
The CY2305/CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 μA current draw for these parts. The CY2309 PLLs shut down in one additional case as shown in Select Input Decoding on page 5.
Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

Features
10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
Zero input-output propagation delay
60-ps typical cycle-to-cycle jitter (high drive)
Multiple low skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 4 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309)
Packages:
8-pin, 150-mil SOIC package (CY2305)
16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
3.3 V operation
Commercial and industrial temperature ranges

Applications
Clock distribution in high-speed systems
PCI bus clock distribution
CPU clock distribution
Test and measurement equipment
Data communications equipment