Texas Instruments CD4033BNSRG4
- Part Number:
- CD4033BNSRG4
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3834041-CD4033BNSRG4
- Description:
- IC COUNTR/DIVIDR DECADE 16SO
- Datasheet:
- CD4033BNSRG4
Texas Instruments CD4033BNSRG4 technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments CD4033BNSRG4.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case16-SOIC (0.209, 5.30mm Width)
- Number of Pins16
- Operating Temperature-55°C~125°C
- PackagingTape & Reel (TR)
- Series4000B
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations16
- TechnologyCMOS
- Voltage - Supply3V~18V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)NOT SPECIFIED
- Number of Functions1
- Supply Voltage5V
- Reflow Temperature-Max (s)NOT SPECIFIED
- Base Part NumberCD4033
- Pin Count16
- Qualification StatusNot Qualified
- Number of Elements1
- Supply Voltage-Min (Vsup)3V
- ResetAsynchronous
- Logic FunctionCounter
- DirectionUp
- Logic TypeCounter, Decade
- Number of Bits per Element5
- Trigger TypePositive Edge
- Propagation Delay (tpd)700 ns
- fmax-Min8 MHz
- Clock Edge Trigger TypePositive Edge
- Count Rate16MHz
- TimingSynchronous
- Height Seated (Max)2mm
- RoHS StatusROHS3 Compliant
CD4033BNSRG4 Overview
The mounting type for this component is surface mount, meaning that it can be easily attached to a surface rather than being inserted into a socket. The terminal position is dual, indicating that there are two terminals for connecting to other components. The terminal form is gull wing, which refers to the shape of the terminals. This particular component has 16 pins, providing multiple connection points. The reset is asynchronous, meaning that it can be triggered at any time, regardless of the clock cycle. The direction is up, indicating that the component should be placed with the terminals facing upwards. The propagation delay is 700 ns, which is the amount of time it takes for the signal to travel through the component. The clock edge trigger type is positive edge, meaning that the signal is triggered on the rising edge of the clock cycle. The maximum height when seated is 2mm, ensuring that it can fit into compact spaces. Lastly, this component is ROHS3 compliant, meeting the environmental standards set by the Restriction of Hazardous Substances Directive.
CD4033BNSRG4 Features
Embedded in the 16-SOIC (0.209, 5.30mm Width) package
5 bits per element
CD4033BNSRG4 Applications
There are a lot of Texas Instruments CD4033BNSRG4 Counters & Dividers applications.
Fixed and programmable counters greater than 10
Communications Digital Frequency Synthesizers;
Up Counters
DIVISION
Dual Up Counters
Control counters
Divide-by-N counting
Time delay circuits
SQUARING
Divide-by"N" counters/frequency synthesizers
The mounting type for this component is surface mount, meaning that it can be easily attached to a surface rather than being inserted into a socket. The terminal position is dual, indicating that there are two terminals for connecting to other components. The terminal form is gull wing, which refers to the shape of the terminals. This particular component has 16 pins, providing multiple connection points. The reset is asynchronous, meaning that it can be triggered at any time, regardless of the clock cycle. The direction is up, indicating that the component should be placed with the terminals facing upwards. The propagation delay is 700 ns, which is the amount of time it takes for the signal to travel through the component. The clock edge trigger type is positive edge, meaning that the signal is triggered on the rising edge of the clock cycle. The maximum height when seated is 2mm, ensuring that it can fit into compact spaces. Lastly, this component is ROHS3 compliant, meeting the environmental standards set by the Restriction of Hazardous Substances Directive.
CD4033BNSRG4 Features
Embedded in the 16-SOIC (0.209, 5.30mm Width) package
5 bits per element
CD4033BNSRG4 Applications
There are a lot of Texas Instruments CD4033BNSRG4 Counters & Dividers applications.
Fixed and programmable counters greater than 10
Communications Digital Frequency Synthesizers;
Up Counters
DIVISION
Dual Up Counters
Control counters
Divide-by-N counting
Time delay circuits
SQUARING
Divide-by"N" counters/frequency synthesizers
CD4033BNSRG4 More Descriptions
Counter ICs CMOS Decade Counter/ Divider
IC COUNTR/DIVIDR DECADE 16SO
CD4026B and CD4033B each consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. Signals peculiar to the CD4033B are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the CD4033B; in the CD4026B these outputs go high only when the DISPLAY ENABLE IN is high. The CD4026B- and CD4033B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
IC COUNTR/DIVIDR DECADE 16SO
CD4026B and CD4033B each consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. Signals peculiar to the CD4033B are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the CD4033B; in the CD4026B these outputs go high only when the DISPLAY ENABLE IN is high. The CD4026B- and CD4033B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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