Analog Devices Inc. AD9511BCPZ

Description
The AD9511 is a multioutput clock distribution IC with an onchip PLL core. It emphasizes low jitter and phase noise for optimal data converter performance. The PLL section includes a programmable reference divider, low noise phase frequency detector, precision charge pump, and programmable feedback divider. By connecting an external VCXO or VCO, frequencies up to 1.6 GHz can be synchronized to the input reference.

Features
Low phase noise phaselocked loop core
Reference input frequencies to 250 MHz
Programmable dualmodulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCPs) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for outputtooutput coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Spacesaving 48lead LFCSP

Applications
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSS, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure