Analog Devices Inc. AD9269BCPZRL7-40
- Part Number:
- AD9269BCPZRL7-40
- Manufacturer:
- Analog Devices Inc.
- Ventron No:
- 3015466-AD9269BCPZRL7-40
- Description:
- IC ADC 16BIT 40MSPS DL 64LFCSP
- Datasheet:
- AD9269BCPZRL7-40
Description
The AD9269 is a 16-bit, dual analog-to-digital converter (ADC) that operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. An optional SPI selectable de correction and quadrature error correction (QEC) feature corrects for de offset, gain, and phase mismatches between the two channels. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments, and voltage reference modes. The AD9269 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
Features
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR: 77.6 dBFS at 9.7 MHz input, 71 dBFS at 200 MHz input
SFDR: 93 dBc at 9.7 MHz input, 80 dBc at 200 MHz input
Low power: 44 mW per channel at 20 MSPS, 100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 Vp-p differential analog input
DNL: -0.5/ 1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and data alignment
Applications
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
1/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
The AD9269 is a 16-bit, dual analog-to-digital converter (ADC) that operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. An optional SPI selectable de correction and quadrature error correction (QEC) feature corrects for de offset, gain, and phase mismatches between the two channels. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments, and voltage reference modes. The AD9269 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
Features
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR: 77.6 dBFS at 9.7 MHz input, 71 dBFS at 200 MHz input
SFDR: 93 dBc at 9.7 MHz input, 80 dBc at 200 MHz input
Low power: 44 mW per channel at 20 MSPS, 100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 Vp-p differential analog input
DNL: -0.5/ 1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and data alignment
Applications
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
1/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Analog Devices Inc. AD9269BCPZRL7-40 technical specifications, attributes, parameters and parts with similar specifications to Analog Devices Inc. AD9269BCPZRL7-40.
- Factory Lead Time20 Weeks
- Lifecycle StatusPRODUCTION (Last Updated: 3 months ago)
- Contact PlatingTin
- Mounting TypeSurface Mount
- Package / Case64-VFQFN Exposed Pad, CSP
- Surface MountYES
- Number of Pins64
- Operating Temperature-40°C~85°C
- PackagingTape & Reel (TR)
- JESD-609 Codee3
- FeatureSimultaneous Sampling
- Pbfree Codeno
- Part StatusActive
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations64
- ECCN Code3A991.C.4
- SubcategoryAnalog to Digital Converters
- Max Power Dissipation142.3mW
- TechnologyCMOS
- Terminal PositionQUAD
- Terminal FormNO LEAD
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage1.8V
- Terminal Pitch0.5mm
- Reflow Temperature-Max (s)30
- Base Part NumberAD9269
- Pin Count64
- Qualification StatusNot Qualified
- Operating Supply Voltage1.8V
- ConfigurationS/H-ADC
- Number of Channels2
- InterfaceParallel, SPI, Serial
- Max Supply Voltage1.9V
- Min Supply Voltage1.7V
- Power Dissipation165.7mW
- Number of Bits16
- Input TypeDifferential
- Min Input Voltage1V
- ArchitecturePipelined
- Max Input Voltage1V
- Converter TypeADC, FLASH METHOD
- Supply TypeAnalog, Digital, Single
- Reference TypeExternal, Internal
- Data InterfaceParallel
- Resolution2 B
- Sampling Rate40 Msps
- Voltage - Supply, Analog1.7V~1.9V
- Voltage - Supply, Digital1.7V~3.6V
- Number of Analog In Channels2
- Sampling Rate (Per Second)40M
- Power Consumption165.7mW
- Linearity Error-Max (EL)0.0084%
- Integral Nonlinearity (INL)5.5 LSB
- Sample and Hold / Track and HoldTRACK
- Input Capacitance6.5pF
- Ratio - S/H:ADC1:1
- Signal to Noise Ratio (SNR)78 dB
- Differential Nonlinearity-0.9 LSB
- Height Seated (Max)1mm
- Length9mm
- Width9mm
- RoHS StatusROHS3 Compliant
- Lead FreeContains Lead
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