Analog Devices Inc. AD807A-155BRRL7
- Part Number:
- AD807A-155BRRL7
- Manufacturer:
- Analog Devices Inc.
- Ventron No:
- 3679828-AD807A-155BRRL7
- Description:
- IC FIBER OPTIC RCVR 16-SOIC
- Datasheet:
- AD807A-155BRRL7
Analog Devices Inc. AD807A-155BRRL7 technical specifications, attributes, parameters and parts with similar specifications to Analog Devices Inc. AD807A-155BRRL7.
- Lifecycle StatusOBSOLETE (Last Updated: 1 week ago)
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case16-SOIC (0.154, 3.90mm Width)
- Number of Pins16
- Operating Temperature-40°C~85°C
- PackagingTape & Reel (TR)
- JESD-609 Codee0
- Pbfree Codeno
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations16
- ECCN Code5A991.B.3
- Terminal FinishTin/Lead (Sn85Pb15)
- ApplicationsSONET;SDH
- HTS Code8542.39.00.01
- SubcategoryATM/SONET/SDH ICs
- Max Power Dissipation170mW
- TechnologyBIPOLAR
- Voltage - Supply4.5V~5.5V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)240
- Number of Functions1
- Supply Voltage5V
- Terminal Pitch1.27mm
- Reach Compliance Codenot_compliant
- Reflow Temperature-Max (s)30
- Base Part NumberAD807
- Pin Count16
- Qualification StatusNot Qualified
- Operating Supply Voltage5V
- Power Supplies5V
- Operating Supply Current39.5mA
- Nominal Supply Current39.5mA
- Power Dissipation170mW
- Data Rate155 Mbps
- ProtocolSDH Sonet
- 3db Bandwidth180MHz
- Number of Drivers/Receivers0/1
- Source Url Status Check Date2013-05-01 14:56:23.44
- Height Seated (Max)1.75mm
- Length9.9mm
- RoHS StatusNon-RoHS Compliant
- Lead FreeContains Lead
AD807A-155BRRL7 Overview
The package or case for this product is 16-SOIC with a width of 0.154 inches (3.90mm). The terminal finish is Tin/Lead (Sn85Pb15) and the HTS code is 8542.39.00.01. The supply voltage for this product is 5V and it has a pin count of 16. The power supplies required for this product is also 5V and the nominal supply current is 39.5mA. The protocol for this product is SDH Sonet and it has a 3db bandwidth of 180MHz. The length of this product is 9.9mm.
AD807A-155BRRL7 Features
Tape & Reel (TR) package
16 pin count
16 pins
5V power supply
AD807A-155BRRL7 Applications
There are a lot of Analog Devices Inc. AD807A-155BRRL7 Drivers/Receivers/Transceivers applications.
Point-to-point networking
Remote controls
Telecom applications
Fiber optic cable connection network
Bar, KTV wireless entertainment
Metro access rings
Carrier phase observations
Portable radio
Wireless transmission
Fiber distributed data interface (FDDI)
The package or case for this product is 16-SOIC with a width of 0.154 inches (3.90mm). The terminal finish is Tin/Lead (Sn85Pb15) and the HTS code is 8542.39.00.01. The supply voltage for this product is 5V and it has a pin count of 16. The power supplies required for this product is also 5V and the nominal supply current is 39.5mA. The protocol for this product is SDH Sonet and it has a 3db bandwidth of 180MHz. The length of this product is 9.9mm.
AD807A-155BRRL7 Features
Tape & Reel (TR) package
16 pin count
16 pins
5V power supply
AD807A-155BRRL7 Applications
There are a lot of Analog Devices Inc. AD807A-155BRRL7 Drivers/Receivers/Transceivers applications.
Point-to-point networking
Remote controls
Telecom applications
Fiber optic cable connection network
Bar, KTV wireless entertainment
Metro access rings
Carrier phase observations
Portable radio
Wireless transmission
Fiber distributed data interface (FDDI)
AD807A-155BRRL7 More Descriptions
FIBER OPTIC RECEIVER WITH QUANTIZER AND CLOCK RECOVERY AND DATA RETIMING
ATM/SONET/SDH Support Circuit, 1-Func, Bipolar, PDSO16
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either 5 V or –5.2 V.
ATM/SONET/SDH Support Circuit, 1-Func, Bipolar, PDSO16
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either 5 V or –5.2 V.
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