IDT, Integrated Device Technology Inc 8701CYLF

Description
The ICS8701 is a low skew, 1, 2 LVCMOS/LVTTL Clock Generator. The low impedance LVCMOS outputs are designed to drive 500 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELX, control the output frequency of each bank. The outputs can be utilized in the 1, 2 or a combination of 1 and 2 modes. The bank enable inputs, BANK ENO:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features
Twenty LVCMOS outputs, 75Ω typical output impedance
One LVCMOS/LVTTL clock input
Maximum output frequency: 250MHz
Bank enable logic allows unused banks to be disabled in reduced fanout applications
Output skew: 250ps (maximum)
Part-to-part skew: 600ps (maximum)
Bank skew: 200ps (maximum)
Multiple frequency skew: 300ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating supply modes
0°C to 70°C ambient operating temperature
Other divide values available on request
Available in both standard and lead-free RoHS compliant packages

Applications
Clock distribution in high-speed digital systems
Datacom and telecom equipment
Networking and storage systems
Industrial and automotive applications