IDT, Integrated Device Technology Inc 8344AYI-01LF

Description
The ICS8344101 is a low voltage, low skew fanout buffer with two selectable differential clock inputs (CLKx, nCLKx). It can accept most standard differential input levels, including LVDS, LVPECL, LVHSTL, and HCSL. The ICS8344101 translates any differential signal level to LVCMOS/LVTTL levels and drives 500 series or parallel terminated transmission lines. It has a maximum output frequency of 100MHz and a synchronous clock enable to eliminate runt pulses on the outputs. The ICS8344101 is characterized at full 3.3V, full 2.5V, and mixed 3.3V input and 2.5V output operating supply modes.

Features
Twentyfour LVCMOS/LVTTL outputs with 72 typical output impedance
Two selectable differential CLKx, nCLKx inputs
Maximum output frequency: 100MHz
Translates any single ended input signal to LVCMOS/LVTTL with resistor bias on CLK input
Synchronous clock enable
Additive phase jitter, RMS: 0.21ps (typical)
Output skew: 200ps (maximum)
Parttopart skew: 900ps (maximum)
Bank skew: 180ps (maximum)
Propagation delay: 5ns (maximum)
Output supply modes:
Core/Output: 3.3V/3.3V, 2.5V/2.5V, 3.3V/2.5V
40°C to 70°C ambient operating temperature
Available in leadfree (RoHS 6) package

Applications
Clock distribution
Redundant clock applications
Board level testing