IDT, Integrated Device Technology Inc 80KSW0003AR

Description
The CPS-8 (IDT80KSW0003) is an 8-port serial RapidIO (SRIO) switch that routes packets for distribution among DSPs, processors, FPGAs, and other SRIO-based devices. It supports serial RapidIO packet switching (unicast, multicast, and optional broadcast) from any of its 8 input ports to any of its 8 output ports.

Features
Interfaces:
8 bidirectional serial RapidIO (SRIO) lanes v1.3
Selectable port speeds: 3.125Gbps, 2.5Gbps, or 1.25Gbps
Configurable port count up to eight 1x ports, two 4x ports, or 4 1x and 1 4x port
Lanes can be configured as individual non-redundant 1x ports, as part of a redundant 1x port, or as part of a 4x port
Support for two separate port rates for each quad
Supports standard 4 levels of priority
Error management support
Interfaces - I²C:
Provides PC port for maintenance and error reporting
Master or Slave Operation
Master allows power-on configuration from external ROM
Master mode configuration with external image compressing and checksum

Performance
20 Gbps of peak switching bandwidth
Non-blocking data flow architecture within each SRIO priority
Very low latency for all packet length and load conditions
Internal queuing buffer and retransmit buffer
Standard receiver based physical layer flow control

Other Features
Configurable for Cut Through or Store And Forward data flow
Device configurable through any of SRIO ports, I²C, or JTAG
Packet Trace: Ability to match the first 160 bits of any packet against up to 4 programmable comparison values to copy the packet to a programmable output trace port
Packet Fitter: Ability to filter the packet based on comparisons against the same 4 programmable values
Supports up to 10 simultaneous multicast masks
Broadcast support
Port Loopback Debug Feature
Software assisted error recovery, supporting hot swap
Ports may be individually turned off to reduce power
PMON counters for monitor and diagnostics
SerDes physical diagnostic registers
Embedded PRBS generation and detection with programmable polynomials support Bit Error Rate (BER) testing
0.13um technology
Low power dissipation
Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6)
Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch