IDT, Integrated Device Technology Inc 5T93GL02PGGI

Description
2.5V differential clock buffer
Userselectable differential input to two LVDS outputs
Reduces loading on preceding driver
Provides efficient clock distribution network
Can translate from differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs
Singleended 3.3V/2.5V LVTTL input can also be used to translate to LVDS outputs
Redundant input capability allows for glitchless changeover from primary to secondary clock source up to 450MHz
Selectable inputs controlled by SEL
Outputs can be asynchronously enabled/disabled
Multiple power and grounds reduce noise

Features
Guaranteed low skew: <50ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and overvoltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
Selectable differential inputs to two LVDS outputs
Powerdown mode
At powerup, FSEL should be LOW
2.5V Voo
40°C to 85°C ambient operating temperature
Available in TSSOP package

Applications
Clock distribution