Microchip Technology SY89871UMI

Description
2.5V/3.3V LVPECL output precision clock divider
Accepts highspeed differential clock input (AC or DCcoupled)
Programmable divider ratio: 2, 4, 8, 16
Matched delay for all outputs, independent of divider setting
Low jitter design: <1pSRMS cycletocycle jitter, <10pspp total jitter
Unique input termination and VT pin for DC and ACcoupled inputs
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: 40°C to 85°C
Available in 16pin (3mm x 3mm) MLP package

Features
Two matcheddelay outputs:
Bank A: undivided passthrough (QA)
Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
Guaranteed AC performance:
>2.5GHz MAX
<250ps t,/t
<670ps tpd (matched delay)
<15ps withindevice skew
Low jitter design:
<1pSRMS cycletocycle jitter
<10pspp total jitter
Power supply: 3.3V or 2.5V
Unique patentpending input termination and VT pin for DC and ACcoupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: 40°C to 85°C

Applications
OC3 to OC192 SONET/SDH applications
Transponders