Texas Instruments SN74LVTH574DW

Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC Tube
TEXAS INSTRUMENTS - SN74LVTH574DW - D-TYPE FLIP FLOP, 3-STATE, SOIC-20
Tube 74LVTH574 e4 74LVTH flip flop 12.8mm 2.7V 4.5ns @ 3.3V 50pF 150MHz
LOGIC, 3.3V OCT FLIP-FLOP, 20SOIC; Flip-Flop Type:D; Propagation Delay:3ns; Frequency:150MHz; Output Current:64mA; Trigger Type:Positive Edge; IC Output Type:Tri State Non Inverted; Supply Voltage Range:2.7V to 3.6V; Logic Case Style:SOIC; No. of Pins:20; Operating Temperature Range:-40°C to 85°C; SVHC:No SVHC (20-Jun-2011); Logic IC Base Number:74574; Logic IC Family:LVTH; Logic IC Function:Octal Edge Triggered D-Type Flip-Flop with 3-State Outputs; Output Type:Tri State Non Inverted; Package / Case:SOIC; Supply Voltage Max:3.6V; Supply Voltage Min:2.7V; Termination Type:SMD
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.