Texas Instruments SN74LVC646ADWR
- Part Number:
- SN74LVC646ADWR
- Manufacturer:
- Texas Instruments
- Ventron No:
- 3703892-SN74LVC646ADWR
- Description:
- IC BUS TRANSCEIVER 8BIT 24SOIC
- Datasheet:
- SN74LVC646ADWR
Texas Instruments SN74LVC646ADWR technical specifications, attributes, parameters and parts with similar specifications to Texas Instruments SN74LVC646ADWR.
- Voltage - Supply:1.65 V ~ 3.6 V
- Supplier Device Package:24-SOIC
- Series:74LVC
- Packaging:Tape & Reel (TR)
- Package / Case:24-SOIC (0.295", 7.50mm Width)
- Output Type:Push-Pull
- Operating Temperature:-40°C ~ 85°C (TA)
- Number of Elements:1
- Number of Bits per Element:8
- Mounting Type:Surface Mount
- Logic Type:Transceiver, Non-Inverting
- Input Type:-
- Current - Output High, Low:24mA, 24mA
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SN74LVC646ADWR More Descriptions
IC BUS TRANSCEIVER 8BIT 24SOIC
IC TXRX NON-INVERT 3.6V 24SOIC
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that are performed with the LVC646A devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at thehigh-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
IC TXRX NON-INVERT 3.6V 24SOIC
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that are performed with the LVC646A devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at thehigh-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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