Texas Instruments SN74AUP1G80DCKR

SN74AUP1G80DCKR Overview
The package is in the form of 5-TSSOP, SC-70-5, SOT-353. D flip flop is embedded in the Tape & Reel (TR) package. It is configured with Invertedas an output. This trigger uses the value Positive Edge. There is an electric part mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis required for its operation. Temperature is set to -40°C~85°C TA. It belongs to the type D-Typeof flip flops. JK flip flop is a part of the 74AUPseries of FPGAs. There should be no greater frequency than 260MHzon its output. Despite external influences, it consumes 0.9μAof quiescent current. A total of 5 terminations have been made. It is a member of the 74AUP1G80 family. The power supply voltage is 1.2V. Its input capacitance is 1.5pF farads. It is a member of the AUP/ULP/Vfamily of D flip flop. The electronic part is mounted in the way of Surface Mount. Basically, it is designed with a set of 5 pins. This device exhibits a clock edge trigger type of Positive Edge. This device is part of the FF/Latchesbase part number family. The flip flop is designed with 1bits. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. Normal operation requires a supply voltage (Vsup) above 0.8V. The superior flexibility is achieved through the use of 1 circuits. This D flip flop is well suited for TR based on its reliable performance. It offers maximum design flexibility with its output current of 20mA. 500nAquiescent current consumed.

SN74AUP1G80DCKR Features
Tape & Reel (TR) package
74AUP series
5 pins
1 Bits

SN74AUP1G80DCKR Applications
There are a lot of Texas Instruments SN74AUP1G80DCKR Flip Flops applications.

Data storage
Set-reset capability
ATE
Automotive
Instrumentation
Buffered Clock
Consumer
Divide a clock signal by 2 or 4
Storage registers
Parallel data storage