ON Semiconductor NB3L8543SDTR2G

Description
The NB3L8543S is a highperformance, lowskew 1to4 LVDS Clock Fanout Buffer. It features a multiplexed input that can be driven by either a differential or singleended input, allowing for the distribution of a lower speed clock along with the highspeed system clock. The CLK_SEL pin selects the differential CLK and CLK inputs when LOW or left open and pulled LOW by the internal pulldown resistor. When CLK_SEL is HIGH, the differential PCLK and PCLK inputs are selected. The common clock enable pin, CLK_EN, is synchronous, ensuring that the outputs are only enabled/disabled when they are already in the LOW state, avoiding the generation of runt clock pulses during asynchronous assertion/deassertion of the clock enable pin. The internal flipflop is clocked on the falling edge of the input clock, and all associated specification limits are referenced to the negative edge of the clock input.

Features
Four Differential LVDS Output Pairs
Two Selectable Differential Clock Inputs
CLK/CLK Can Accept LVPECL, LVDS, HCSL, SSTL, and HSTL
PCLK/PCLK Can Accept LVPECL, LVDS, CML, and SSTL
Maximum Output Frequency: 650 MHz
Additive Phase Jitter, RMS: 50 fs (typical)
Output Skew: 40 ps (maximum)
Parttopart Skew: 200 ps (maximum)
Propagation Delay: 1.9 ns (maximum)
Operating Range: VDD = 2.5 V ±5% or 3.3 V ±10%
40°C to 85°C Ambient Operating Temperature Range
TSSOP20 Package

Applications
Clock distribution in highspeed systems
Datacom and telecom applications
Networking equipment
Test and measurement equipment
Industrial automation