ON Semiconductor NB2308AI1D

Description
The NB2308A is a 3.3 V zero delay clock buffer designed to distribute high-speed clocks. It features an on-chip PLL that locks to an input clock on the REF pin. The PLL feedback is driven to the FBK pin, which can be obtained from one of the outputs. The input-to-output propagation delay is less than 250 ps, and the output-to-output skew is less than 200 ps.
The NB2308A has two banks of four outputs each, controlled by select inputs. Bank B can be three-stated if all output clocks are not required. The select input also allows the input clock to be directly applied to the outputs for testing purposes.
Multiple NB2308A devices can accept the same input clock and distribute it with a skew of less than 700 ps between outputs.

Features
Zero input-output propagation delay, adjustable by capacitive load on FBK input
Multiple configurations (see NB2308A Configurations Table)
Input frequency range: 15 MHz to 133 MHz
Multiple low-skew outputs
Output-output skew less than 200 ps
Device-device skew less than 700 ps
Two banks of four outputs, three-stateable by two select inputs
Less than 200 ps cycle-to-cycle jitter
Available in 16-pin SOIC and TSSOP packages
3.3 V operation
Guaranteed across commercial and industrial temperature ranges
Advanced 0.35 µ CMOS technology
Pb-free devices

Applications
High-speed clock distribution
Clock buffering
Clock synthesis
Clock recovery
Clock conditioning
Clock fanout
Clock multiplexing
Clock gating
Clock shaping
Clock jitter reduction