ON Semiconductor NB2304AI1DR2G

Description
The NB2304A is a 3.3 V zero delay buffer designed to distribute highspeed clocks in various applications, including PCs, workstations, datacom, and telecom. It features an onchip PLL that locks to an input clock on the REF pin. The PLL feedback is driven to the FBK pin, which can be obtained from one of the outputs. The inputtooutput propagation delay is less than 250 ps, and the outputtooutput skew is less than 200 ps.

Features
Zero inputoutput propagation delay, adjustable by capacitive load on FBK input
Multiple configurations (refer to NB2304A Configurations Table)
Input frequency range: 15 MHz to 133 MHz
Multiple lowskew outputs
Outputoutput skew < 200 ps
Devicedevice skew < 500 ps
Two banks of four outputs
Less than 200 ps cycletocycle jitter (1, 1H, SH)
Available in spacesaving, 8pin 150 mil SOIC package
3.3 V operation
Advanced 0.35 μ CMOS technology
Guaranteed across commercial and industrial temperature ranges

Applications
Highspeed clock distribution in PCs, workstations, datacom, and telecom applications
Clock buffering and distribution in highperformance systems
Clock synchronization and skew reduction