ON Semiconductor MC10EL15DR2G

Description
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device only. For singleended input conditions, the unused differential input is connected to Vag as a switching reference voltage. Vag may also rebias AC coupled inputs. When used, decouple VBB and Vcc via a 0.01 μF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the highspeed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
The 100 series contains temperature compensation.

Features
50 ps OutputtoOutput Skew
Synchronous Enable/Disable
Multiplexed Clock Input
PECL Mode Operating Range:
Vcc 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range:
Vcc 0 V with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors on CLKS, SCLK, SEL, and EN
PbFree, Halogen Free, and RoHS Compliant

Applications
Clock distribution in highspeed systems
Scan and test clock distribution
Multiplexing of multiple clock sources