ON Semiconductor MC100LVE210FNR2
- Part Number:
- MC100LVE210FNR2
- Manufacturer:
- ON Semiconductor
- Ventron No:
- 2975833-MC100LVE210FNR2
- Description:
- IC CLK BUF 1:4/1:5 700GHZ 28PLCC
- Datasheet:
- MC100LVE210 Series
Description
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed for clock distribution. It features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device has fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, reducing the skew between the two fundamental signals from a parttopart skew down to an outputtooutput skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task.
Features
200 ps ParttoPart Skew
50 ps Typical OutputtoOutput Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
Applications
High performance clock distribution in 3.3 V systems
Clock distribution across the backplane or the board
PECL mode operating range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL mode operating range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed for clock distribution. It features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device has fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, reducing the skew between the two fundamental signals from a parttopart skew down to an outputtooutput skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task.
Features
200 ps ParttoPart Skew
50 ps Typical OutputtoOutput Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
Applications
High performance clock distribution in 3.3 V systems
Clock distribution across the backplane or the board
PECL mode operating range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL mode operating range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
ON Semiconductor MC100LVE210FNR2 technical specifications, attributes, parameters and parts with similar specifications to ON Semiconductor MC100LVE210FNR2.
- MountSurface Mount
- Mounting TypeSurface Mount
- Package / Case28-LCC (J-Lead)
- Number of Pins28
- Operating Temperature-40°C~85°C
- PackagingTape & Reel (TR)
- Published2006
- Series100LVE
- JESD-609 Codee0
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations28
- Terminal FinishTin/Lead (Sn/Pb)
- Additional FeatureNECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V
- SubcategoryClock Drivers
- TechnologyECL
- Voltage - Supply3V~3.8V
- Terminal PositionQUAD
- Terminal FormJ BEND
- Peak Reflow Temperature (Cel)240
- Number of Functions2
- Supply Voltage3.3V
- Reach Compliance Codenot_compliant
- Reflow Temperature-Max (s)30
- Base Part NumberMC100LVE210
- OutputECL, PECL
- Pin Count28
- Number of Outputs18
- Qualification StatusNot Qualified
- Supply Voltage-Max (Vsup)3.8V
- Power Supplies-3.3V
- Supply Voltage-Min (Vsup)3V
- Number of Circuits2
- Propagation Delay900 ps
- Frequency (Max)700MHz
- InputECL, PECL
- Ratio - Input:Output1:4, 1:5
- Differential - Input:OutputYes/Yes
- Same Edge Skew-Max (tskwd)0.075 ns
- Height Seated (Max)4.57mm
- Length11.505mm
- Width11.505mm
- RoHS StatusNon-RoHS Compliant
- Lead FreeContains Lead
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