NXP USA Inc. MC100ES6226FA

Description
The MC100ES6226 is a differential clock distribution buffer and clock divider designed for highperformance clock distribution systems. It features a fully differential architecture from input to output, SiGe technology for nearzero output skew, and supports clock frequencies up to 3 GHz. The device operates from a single 3.3V or 2.5V supply and has a maximum output skew of 35 ps within an output bank and 50 ps across the device. It also supports synchronous output enable to eliminate output runt pulses and metastability.

Features
Fully differential architecture
SiGe technology for nearzero output skew
Selectable 1:1 or 1:2 frequency outputs
LVPECL compatible differential clock inputs and outputs
LVCMOS compatible control inputs
Single 3.3V or 2.5V supply
Max. 35 ps maximum output skew (within output bank)
Max. 50 ps maximum device skew
Supports DC operation and up to 3 GHz (typ.) clock signals
Synchronous output enable eliminating output runt pulse generation and metastability
Standard 32 lead LQFP package
Industrial temperature range

Applications
Primary clock distribution systems on backplanes of highperformance computer, networking, and telecommunication systems
Onboard clocking of OC3, OC12, and OC48 speed communication systems