IDT, Integrated Device Technology Inc IDT5T995APPGI

Description
The IDT5T995/A is a 2.5V PLL-based clock driver designed for high-performance computing and data communications applications. It features programmable skew outputs, allowing outputs to lead or lag the reference input signal. The device has eight programmable skew outputs in four banks of two, with skew controlled by 3-level input signals.
The feedback input enables divide-by-functionality from 1 to 12, providing frequency multiplication without using divided outputs for feedback. The synchronous output enable (SOE) pin enables or disables all outputs except 2Q0 and 2Q1. The LOCK output indicates when phase lock has been achieved.
The IDT5T995/A has LVTTL outputs with 12mA balanced drive outputs and low jitter (<100ps cycle-to-cycle). It also features a power-down mode and is available in standard and A speed grades.

Features
3.3V tolerant reference input
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Input frequency:
Std: 2MHz to 160MHz
A: 2MHz to 200MHz
Output frequency:
Std: 6MHz to 160MHz
A: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection (multiply/divider ratios of (1-6, 8, 10, 12)/(2, 4))
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low jitter: <100ps cycle-to-cycle
Power-down mode
Lock indicator
Standard and A speed grades
Available in TQFP package

Applications
High-performance computing
Data communications
DSP applications