Fairchild/ON Semiconductor GTLP16616MTDX

17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
Bus XCVR Single 17-CH 3-ST 56-Pin TSSOP W T/R
3.15V~3.45V 17 TSSOP-56 Latches ROHS
GULL WING Surface Mount RoHS Compliant Bidirectional Universal Bus Transceiver -40C~85C 32mA 32mA 3.15V~3.45V 0.5mm
IC TRANSCVR 17BIT N-INV 56TSSOP
17 BIT TTL/GTLP BUS TX W BUF CLK
The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLPÕs reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. FairchildÕs GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.